Invention Application
- Patent Title: DECODING SYSTEM AND PHYSICAL LAYOUT FOR ANALOG NEURAL MEMORY IN DEEP LEARNING ARTIFICIAL NEURAL NETWORK
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Application No.: US16503355Application Date: 2019-07-03
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Publication No.: US20200342938A1Publication Date: 2020-10-29
- Inventor: HIEU VAN TRAN , THUAN VU , STANLEY HONG , STEPHEN TRINH , ANH LY , HAN TRAN , KHA NGUYEN , HIEN PHAM
- Applicant: Silicon Storage Technology, Inc.
- Assignee: Silicon Storage Technology, Inc.
- Current Assignee: Silicon Storage Technology, Inc.
- Main IPC: G11C11/56
- IPC: G11C11/56 ; G11C11/16 ; G11C11/4074 ; G06F17/16 ; G06N3/06
Abstract:
Various embodiments of word line decoders, control gate decoders, bit line decoders, low voltage row decoders, and high voltage row decoders and various types of physical layout designs for non-volatile flash memory arrays in an analog neural system are disclosed. Shared and segmented embodiments of high voltage row decoders are disclosed.
Public/Granted literature
- US11423979B2 Decoding system and physical layout for analog neural memory in deep learning artificial neural network Public/Granted day:2022-08-23
Information query
