公开(公告)号：US20240127890A1

公开(公告)日：2024-04-18

申请号：US18536147

申请日：2023-12-11

申请人： Silicon Storage Technology, Inc.

发明人： Hieu Van Tran ,  THUAN VU ,  STANLEY HONG ,  STEPHEN TRINH ,  ANH LY ,  NHAN DO ,  MARK REITEN

IPC分类号： G11C16/08 ,  G11C11/54 ,  G11C16/24

CPC分类号： G11C16/08 ,  G11C11/54 ,  G11C16/24 ,  G11C2216/04

摘要： In one example, a non-volatile memory system, comprises an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain; a plurality of bit lines, each of the plurality of bit lines coupled to the drain or each non-volatile memory cell in a column of non-volatile memory cells; a source line coupled to the source of each non-volatile memory cell; and an adaptive bias decoder for providing a voltage to an erase gate line of the array during an operation, wherein the adaptive bias decoder adjusts the voltage provided to the erase gate line in response to changes in a voltage of the source line.

公开(公告)号：US20220336010A1

公开(公告)日：2022-10-20

申请号：US17856839

申请日：2022-07-01

申请人： Silicon Storage Technology, Inc.

发明人： Hieu Van Tran ,  THUAN VU ,  STEPHEN TRINH ,  STANLEY HONG ,  ANH LY ,  STEVEN LEMKE ,  VIPIN TIWARI ,  NHAN DO

IPC分类号： G11C11/54 ,  G11C16/04 ,  G11C16/08 ,  G11C16/16 ,  G11C16/34 ,  G06N3/063 ,  G11C16/10

摘要： Numerous examples for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed. In one example, an analog neural memory system comprises an array of non-volatile memory cells arranged into rows and columns, each non-volatile memory cell comprising a word line terminal, a bit line terminal, and an erase gate terminal; a plurality of word lines, each word line coupled to word line terminals of a row of non-volatile memory cells; a plurality of bit lines, each bit line coupled to bit line terminals of a column of non-volatile memory cells; and a plurality of erase gate enable transistors, each erase gate enable transistor coupled to erase gate terminals of a word of non-volatile memory cells.

公开(公告)号：US20240104164A1

公开(公告)日：2024-03-28

申请号：US18080545

申请日：2022-12-13

申请人： Silicon Storage Technology, Inc.

发明人： HIEU VAN TRAN ,  STEPHEN TRINH ,  STANLEY HONG ,  THUAN VU ,  DUC NGUYEN ,  HIEN HO PHAM

IPC分类号： G06F17/16 ,  G06N3/063

CPC分类号： G06F17/16 ,  G06N3/063

摘要： Numerous examples are disclosed of verification circuitry and associated methods in an artificial neural network. In one example, a system comprises a vector-by-matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns, the non-volatile memory cells respectively capable of storing one of N possible levels corresponding to one of N possible currents, and a plurality of output blocks to receive current from respective columns of the vector-by-matrix multiplication array and generate voltages during a verify operation of the vector-by-matrix multiplication and generate digital outputs during a read operation of the vector-by-matrix multiplication.

公开(公告)号：US20240095509A1

公开(公告)日：2024-03-21

申请号：US18520500

申请日：2023-11-27

申请人： Silicon Storage Technology, Inc.

发明人： Hieu Van Tran ,  STANLEY HONG ,  ANH LY ,  THUAN VU ,  HIEN PHAM ,  KHA NGUYEN ,  HAN TRAN

IPC分类号： G06N3/065 ,  G06F17/16 ,  G06N3/04

CPC分类号： G06N3/065 ,  G06F17/16 ,  G06N3/04

摘要： In one example, a neural network device comprises a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, wherein the first plurality of synapses comprises a plurality of memory cells, each of the plurality of memory cells configured to store a weight value corresponding to a number of electrons on its floating gate and the plurality of memory cells are configured to generate the first plurality of outputs based upon the first plurality of inputs and the stored weight values.

公开(公告)号：US20230048411A1

公开(公告)日：2023-02-16

申请号：US17520396

申请日：2021-11-05

申请人： Silicon Storage Technology, Inc.

发明人： Hieu Van Tran ,  KHA NGUYEN ,  THUAN VU ,  HIEN PHAM ,  STANLEY HONG ,  STEPHEN TRINH

IPC分类号： G06N3/063 ,  G06F17/16 ,  H03M1/46

摘要： Numerous embodiments of input circuitry for an analog neural memory in a deep learning artificial neural network are disclosed.

公开(公告)号：US20240282351A1

公开(公告)日：2024-08-22

申请号：US18195322

申请日：2023-05-09

申请人： Silicon Storage Technology, Inc.

发明人： HIEU VAN TRAN ,  HOA VU ,  STEPHEN TRINH ,  STANLEY HONG ,  THUAN VU ,  NGHIA LE ,  DUC NGUYEN ,  HIEN PHAM

IPC分类号： G11C7/16 ,  G11C7/12 ,  G11C7/14

CPC分类号： G11C7/16 ,  G11C7/12 ,  G11C7/14

摘要： In one example, a system comprises an array of non-volatile memory cells arranged into rows and columns, the array comprising a first bit line coupled to a first column of non-volatile memory cells and a second bit line coupled to a second column of non-volatile memory cells; and an output block coupled to the array, the output block comprising: a current-to-voltage converter to convert a first current on the first bit line into a first voltage and to convert a second current on the second bit line into a second voltage; and an analog-to-digital converter to convert one or more of the first voltage and the second voltage into a set of output bits.

公开(公告)号：US20240095508A1

公开(公告)日：2024-03-21

申请号：US18520277

申请日：2023-11-27

申请人： Silicon Storage Technology, inc.

发明人： HIEU VAN TRAN ,  STANLEY HONG ,  AHN LY ,  THUAN VU ,  HIEN PHAM ,  KHA NGUYEN ,  HAN TRAN

IPC分类号： G06N3/065 ,  G06F17/16 ,  G06N3/04

CPC分类号： G06N3/065 ,  G06F17/16 ,  G06N3/04

摘要： In one example, a system comprises a vector-by-matrix multiplication array comprising non-volatile memory cells organized into rows and columns; a plurality of word lines coupled respectively to rows of the vector-by-matrix multiplication array; and a word line driver coupled to the plurality of word lines, the word line driver comprising a plurality of select transistors coupled to a common control line and the plurality of word lines, and a plurality of bias transistors coupled to the plurality of select transistors and capable of providing a bias voltage to a single select transistor in the plurality of select transistors or to all of plurality of select transistors in response to control signals.

公开(公告)号：US20230325646A1

公开(公告)日：2023-10-12

申请号：US17848381

申请日：2022-06-23

申请人： Silicon Storage Technology, Inc.

发明人： Hieu Van Tran ,  THUAN VU ,  STANLEY HONG ,  STEPHEN TRINH ,  STEVEN LEMKE ,  LOUISA SCHNEIDER ,  NHAN DO

IPC分类号： G06N3/063

CPC分类号： G06N3/063

摘要： Numerous examples are disclosed of an artificial neural network comprising a plurality of reference arrays used for configuration of a vector-by-matrix multiplication array. In one example, a system comprises a vector-by-matrix multiplication array in an artificial neural network; and a plurality of reference arrays characterized by different I-V curves, wherein one or more of the plurality of reference arrays are used to generate input voltage the vector-by-matrix multiplication array during operation.

公开(公告)号：US20220336011A1

公开(公告)日：2022-10-20

申请号：US17857113

申请日：2022-07-04

申请人： Silicon Storage Technology, Inc.

发明人： Hieu Van Tran ,  THUAN VU ,  STEPHEN TRINH ,  STANLEY HONG ,  ANH LY ,  STEVEN LEMKE ,  VIPIN TIWARI ,  NHAN DO

IPC分类号： G11C11/54 ,  G11C16/04 ,  G11C16/08 ,  G11C16/16 ,  G11C16/34 ,  G06N3/063 ,  G11C16/10

摘要： Numerous examples for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed. In one example, a method comprises programming a word or page of non-volatile memory cells in an analog neural memory system; and identifying any fast bits in the word or page of non-volatile memory cells.

公开(公告)号：US20210342682A1

公开(公告)日：2021-11-04

申请号：US17367633

申请日：2021-07-06

申请人： Silicon Storage Technology, Inc.

发明人： Hieu Van Tran ,  STANLEY HONG ,  ANH LY ,  THUAN VU ,  HIEN PHAM ,  KHA NGUYEN ,  HAN TRAN

IPC分类号： G06N3/063 ,  G06N3/04 ,  G06F17/16

摘要： Numerous embodiments of decoders for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. The decoders include bit line decoders, word line decoders, control gate decoders, source line decoders, and erase gate decoders. In certain embodiments, a high voltage version and a low voltage version of a decoder is used.