公开(公告)号：US20240127890A1

公开(公告)日：2024-04-18

申请号：US18536147

申请日：2023-12-11

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  THUAN VU ,  STANLEY HONG ,  STEPHEN TRINH ,  ANH LY ,  NHAN DO ,  MARK REITEN

IPC: G11C16/08 ,  G11C11/54 ,  G11C16/24

CPC classification number: G11C16/08 ,  G11C11/54 ,  G11C16/24 ,  G11C2216/04

Abstract: In one example, a non-volatile memory system, comprises an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain; a plurality of bit lines, each of the plurality of bit lines coupled to the drain or each non-volatile memory cell in a column of non-volatile memory cells; a source line coupled to the source of each non-volatile memory cell; and an adaptive bias decoder for providing a voltage to an erase gate line of the array during an operation, wherein the adaptive bias decoder adjusts the voltage provided to the erase gate line in response to changes in a voltage of the source line.

公开(公告)号：US20220336010A1

公开(公告)日：2022-10-20

申请号：US17856839

申请日：2022-07-01

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  THUAN VU ,  STEPHEN TRINH ,  STANLEY HONG ,  ANH LY ,  STEVEN LEMKE ,  VIPIN TIWARI ,  NHAN DO

IPC: G11C11/54 ,  G11C16/04 ,  G11C16/08 ,  G11C16/16 ,  G11C16/34 ,  G06N3/063 ,  G11C16/10

Abstract: Numerous examples for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed. In one example, an analog neural memory system comprises an array of non-volatile memory cells arranged into rows and columns, each non-volatile memory cell comprising a word line terminal, a bit line terminal, and an erase gate terminal; a plurality of word lines, each word line coupled to word line terminals of a row of non-volatile memory cells; a plurality of bit lines, each bit line coupled to bit line terminals of a column of non-volatile memory cells; and a plurality of erase gate enable transistors, each erase gate enable transistor coupled to erase gate terminals of a word of non-volatile memory cells.

公开(公告)号：US20240104164A1

公开(公告)日：2024-03-28

申请号：US18080545

申请日：2022-12-13

Applicant: Silicon Storage Technology, Inc.

Inventor： HIEU VAN TRAN ,  STEPHEN TRINH ,  STANLEY HONG ,  THUAN VU ,  DUC NGUYEN ,  HIEN HO PHAM

IPC: G06F17/16 ,  G06N3/063

CPC classification number: G06F17/16 ,  G06N3/063

Abstract: Numerous examples are disclosed of verification circuitry and associated methods in an artificial neural network. In one example, a system comprises a vector-by-matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns, the non-volatile memory cells respectively capable of storing one of N possible levels corresponding to one of N possible currents, and a plurality of output blocks to receive current from respective columns of the vector-by-matrix multiplication array and generate voltages during a verify operation of the vector-by-matrix multiplication and generate digital outputs during a read operation of the vector-by-matrix multiplication.

公开(公告)号：US20230048411A1

公开(公告)日：2023-02-16

申请号：US17520396

申请日：2021-11-05

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  KHA NGUYEN ,  THUAN VU ,  HIEN PHAM ,  STANLEY HONG ,  STEPHEN TRINH

IPC: G06N3/063 ,  G06F17/16 ,  H03M1/46

Abstract: Numerous embodiments of input circuitry for an analog neural memory in a deep learning artificial neural network are disclosed.

公开(公告)号：US20240282351A1

公开(公告)日：2024-08-22

申请号：US18195322

申请日：2023-05-09

Applicant: Silicon Storage Technology, Inc.

Inventor： HIEU VAN TRAN ,  HOA VU ,  STEPHEN TRINH ,  STANLEY HONG ,  THUAN VU ,  NGHIA LE ,  DUC NGUYEN ,  HIEN PHAM

IPC: G11C7/16 ,  G11C7/12 ,  G11C7/14

CPC classification number: G11C7/16 ,  G11C7/12 ,  G11C7/14

Abstract: In one example, a system comprises an array of non-volatile memory cells arranged into rows and columns, the array comprising a first bit line coupled to a first column of non-volatile memory cells and a second bit line coupled to a second column of non-volatile memory cells; and an output block coupled to the array, the output block comprising: a current-to-voltage converter to convert a first current on the first bit line into a first voltage and to convert a second current on the second bit line into a second voltage; and an analog-to-digital converter to convert one or more of the first voltage and the second voltage into a set of output bits.

公开(公告)号：US20230325646A1

公开(公告)日：2023-10-12

申请号：US17848381

申请日：2022-06-23

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  THUAN VU ,  STANLEY HONG ,  STEPHEN TRINH ,  STEVEN LEMKE ,  LOUISA SCHNEIDER ,  NHAN DO

IPC: G06N3/063

CPC classification number: G06N3/063

Abstract: Numerous examples are disclosed of an artificial neural network comprising a plurality of reference arrays used for configuration of a vector-by-matrix multiplication array. In one example, a system comprises a vector-by-matrix multiplication array in an artificial neural network; and a plurality of reference arrays characterized by different I-V curves, wherein one or more of the plurality of reference arrays are used to generate input voltage the vector-by-matrix multiplication array during operation.

公开(公告)号：US20220336011A1

公开(公告)日：2022-10-20

申请号：US17857113

申请日：2022-07-04

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  THUAN VU ,  STEPHEN TRINH ,  STANLEY HONG ,  ANH LY ,  STEVEN LEMKE ,  VIPIN TIWARI ,  NHAN DO

IPC: G11C11/54 ,  G11C16/04 ,  G11C16/08 ,  G11C16/16 ,  G11C16/34 ,  G06N3/063 ,  G11C16/10

Abstract: Numerous examples for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed. In one example, a method comprises programming a word or page of non-volatile memory cells in an analog neural memory system; and identifying any fast bits in the word or page of non-volatile memory cells.

公开(公告)号：US20200342938A1

公开(公告)日：2020-10-29

申请号：US16503355

申请日：2019-07-03

Applicant: Silicon Storage Technology, Inc.

Inventor： HIEU VAN TRAN ,  THUAN VU ,  STANLEY HONG ,  STEPHEN TRINH ,  ANH LY ,  HAN TRAN ,  KHA NGUYEN ,  HIEN PHAM

IPC: G11C11/56 ,  G11C11/16 ,  G11C11/4074 ,  G06F17/16 ,  G06N3/06

Abstract: Various embodiments of word line decoders, control gate decoders, bit line decoders, low voltage row decoders, and high voltage row decoders and various types of physical layout designs for non-volatile flash memory arrays in an analog neural system are disclosed. Shared and segmented embodiments of high voltage row decoders are disclosed.

公开(公告)号：US20240338144A1

公开(公告)日：2024-10-10

申请号：US18212066

申请日：2023-06-20

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  STEPHEN TRINH ,  HOA VU ,  STANLEY HONG ,  THUAN VU

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/062 ,  G06F3/0679 ,  G11C16/08

Abstract: Numerous examples are disclosed of a masking circuit for inputs and outputs in a neural network array. In one example, a system comprises a neural network array comprising a plurality of non-volatile memory cells arranged into rows and columns; and row circuits for respective rows in the neural network array, the row circuits comprising a masking circuit to prevent an application of a sparse input to one or more rows in the array when a condition is satisfied.

公开(公告)号：US20240112003A1

公开(公告)日：2024-04-04

申请号：US18077993

申请日：2022-12-08

Applicant: Silicon Storage Technology, Inc.

Inventor： HIEU VAN TRAN ,  STEPHEN TRINH ,  STANLEY HONG ,  THUAN VU ,  NGHIA LE ,  HIEN PHAM

IPC: G06N3/063 ,  G06F5/01 ,  G06F7/501

CPC classification number: G06N3/063 ,  G06F5/01 ,  G06F7/501

Abstract: Numerous examples are disclosed of output circuitry and associated methods in an artificial neural network. In one example, a system comprises an array of non-volatile memory cells arranged into rows and columns, an output block to convert current from columns of the array into a first digital output during a first time period and a second digital output during a second time period, a first output register to store the first digital output during the first time period and to output the stored first digital output during the second time period, and a second output register to store the second digital output during the second time period and to output the stored second digital output during a third time period.