Invention Application
- Patent Title: DIE-TO-WAFER BONDING STRUCTURE AND SEMICONDUCTOR PACKAGE USING THE SAME
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Application No.: US16985445Application Date: 2020-08-05
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Publication No.: US20210104482A1Publication Date: 2021-04-08
- Inventor: Jiseok Hong , Unbyoung Kang , Myungsung Kang , Taehun Kim , Sangcheon Park , Hyuekjae Lee , Jihwan Hwang
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Suwon-si
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si
- Priority: KR10-2019-0123973 20191007
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L21/66 ; H01L25/00 ; H01L25/065

Abstract:
According to an aspect of the inventive concept, there is provided a die-to-wafer bonding structure including a die having a first test pad, a first bonding pad formed on the first test pad, and a first insulating layer, the first bonding pad penetrates the first insulating layer. The structure may further include a wafer having a second test pad, a second bonding pad formed on the second test pad, and a second insulating layer, the second bonding pad penetrates the second insulating layer. The structure may further include a polymer layer surrounding all side surfaces of the first bonding pad and all side surfaces of the second bonding pad, the polymer layer being arranged between the die and the wafer. Additionally, the wafer and the die may be bonded together.
Public/Granted literature
- US11289438B2 Die-to-wafer bonding structure and semiconductor package using the same Public/Granted day:2022-03-29
Information query
IPC分类: