公开(公告)号：US12080691B2

公开(公告)日：2024-09-03

申请号：US17585122

申请日：2022-01-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungwoo Park ,  Heonwoo Kim ,  Sangcheon Park ,  Wonil Lee

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L25/105 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/37001

Abstract: A semiconductor device including an interposer including a central region and an edge region entirely surrounding the central region, wherein the interposer includes a wiring structure disposed in the first region and a metal structure disposed continuously within the entirety of the second region, a first semiconductor chip mounted in the central region and connected to the wiring structure, and a second semiconductor chip mounted in the central region adjacent to the first semiconductor chip and connected to the second wiring structure.

公开(公告)号：US11621247B2

公开(公告)日：2023-04-04

申请号：US17203909

申请日：2021-03-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangcheon Park ,  Youngmin Lee

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/12 ,  H01L23/00

Abstract: A semiconductor package includes: a first structure having a first insulating layer disposed on one surface, and first electrode pads and first dummy pads penetrating through the first insulating layer, a second structure having a second insulating layer having the other surface bonded to the one surface and the first insulating layer and disposed on the other surface, and second electrode pads and second dummy pads that penetrate through the second insulating layer, the second electrode pads being bonded to the first electrode pads, respectively, and the second dummy pads being bonded to the first dummy pads, respectively. In the semiconductor chip, ratios of surface areas per unit area of the first and second dummy pads to the first and second insulating layers on the one surface and the other surface gradually decrease toward sides of the first and second structures.

公开(公告)号：US20250015026A1

公开(公告)日：2025-01-09

申请号：US18897635

申请日：2024-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuekjae Lee ,  Jongho Lee ,  Jihoon Kim ,  Taehun Kim ,  Sangcheon Park ,  Jinkyeong Seol ,  Sanghoon Lee

IPC: H01L23/00 ,  H01L21/56 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor package includes a first connection structure, a first semiconductor chip on an upper surface of the first connection structure, a first molding layer on the upper surface of the first connection structure and surrounding the first semiconductor chip, a first bond pad on the first semiconductor chip, a first bond insulation layer on the first semiconductor chip and the first molding layer and surrounding the first bond pad, a second bond pad directly contacting the first bond pad, a second bond insulation layer surrounding the second bond pad; and a second semiconductor chip on the second bond pad and the second bond insulation layer.

公开(公告)号：US12094867B2

公开(公告)日：2024-09-17

申请号：US18356350

申请日：2023-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangcheon Park ,  Youngmin Lee

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/544

CPC classification number: H01L25/18 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/544 ,  H01L24/08 ,  H01L2223/54426 ,  H01L2224/0224 ,  H01L2224/08145

Abstract: A semiconductor package includes: a first semiconductor chip including a plurality of front surface pads disposed on a first active surface of a first semiconductor substrate, at least one penetrating electrode penetrating at least a portion of the first semiconductor substrate and connected to the front surface pads, a first rear surface cover layer disposed on a first inactive surface of the first semiconductor substrate, a first rear surface dummy conductive layer penetrating a portion of the first rear surface cover layer; a second semiconductor chip including a second front surface cover layer disposed on a second active surface of a second semiconductor substrate, and a second front surface dummy conductive layer penetrating a portion of the second front surface cover layer; and at least one first bonded pad penetrating the first rear surface cover layer and the second front surface cover layer.

公开(公告)号：US11749662B2

公开(公告)日：2023-09-05

申请号：US17505040

申请日：2021-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangcheon Park ,  Youngmin Lee

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/544

CPC classification number: H01L25/18 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/544 ,  H01L24/08 ,  H01L2223/54426 ,  H01L2224/0224 ,  H01L2224/08145

Abstract: A semiconductor package includes: a first semiconductor chip including a plurality of front surface pads disposed on a first active surface of a first semiconductor substrate, at least one penetrating electrode penetrating at least a portion of the first semiconductor substrate and connected to the front surface pads, a first rear surface cover layer disposed on a first inactive surface of the first semiconductor substrate, a first rear surface dummy conductive layer penetrating a portion of the first rear surface cover layer; a second semiconductor chip including a second front surface cover layer disposed on a second active surface of a second semiconductor substrate, and a second front surface dummy conductive layer penetrating a portion of the second front surface cover layer; and at least one first bonded pad penetrating the first rear surface cover layer and the second front surface cover layer.

公开(公告)号：US11289438B2

公开(公告)日：2022-03-29

申请号：US16985445

申请日：2020-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiseok Hong ,  Unbyoung Kang ,  Myungsung Kang ,  Taehun Kim ,  Sangcheon Park ,  Hyuekjae Lee ,  Jihwan Hwang

IPC: H01L29/40 ,  H01L23/00 ,  H01L21/66 ,  H01L25/065 ,  H01L25/00 ,  H01L23/48

Abstract: According to an aspect of the inventive concept, there is provided a die-to-wafer bonding structure including a die having a first test pad, a first bonding pad formed on the first test pad, and a first insulating layer, the first bonding pad penetrates the first insulating layer. The structure may further include a wafer having a second test pad, a second bonding pad formed on the second test pad, and a second insulating layer, the second bonding pad penetrates the second insulating layer. The structure may further include a polymer layer surrounding all side surfaces of the first bonding pad and all side surfaces of the second bonding pad, the polymer layer being arranged between the die and the wafer. Additionally, the wafer and the die may be bonded together.

公开(公告)号：US20240413125A1

公开(公告)日：2024-12-12

申请号：US18677392

申请日：2024-05-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seho You ,  Sangcheon Park

IPC: H01L25/065 ,  G02B6/42 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/07

Abstract: Provided is a semiconductor package including a package substrate, a connection substrate mounted on the package substrate, and including a first conductive connection structure, a first integrated circuit device mounted on the package substrate, and a second integrated circuit device disposed on the connection substrate and the first integrated circuit device, and including a first portion overlapping the first integrated circuit device and a second portion overlapping the connection substrate, wherein one of the first integrated circuit device and the second integrated circuit device includes a photonic integrated circuit device to which an optical fiber is attached, and the other of the first integrated circuit device and the second integrated circuit device includes an electronic integrated circuit device, and wherein the second integrated circuit device is electrically connected to the package substrate via the first conductive connection structure of the connection substrate.

公开(公告)号：US12132019B2

公开(公告)日：2024-10-29

申请号：US18151622

申请日：2023-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuekjae Lee ,  Jongho Lee ,  Jihoon Kim ,  Taehun Kim ,  Sangcheon Park ,  Jinkyeong Seol ,  Sanghoon Lee

IPC: H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L24/06 ,  H01L21/561 ,  H01L24/05 ,  H01L24/08 ,  H01L24/13 ,  H01L24/32 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/05025 ,  H01L2224/05073 ,  H01L2224/05562 ,  H01L2224/05564 ,  H01L2224/06182 ,  H01L2224/08121 ,  H01L2224/08145 ,  H01L2224/08148 ,  H01L2224/08225 ,  H01L2224/13024 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/80895 ,  H01L2224/83099 ,  H01L2224/8389 ,  H01L2224/92142 ,  H01L2225/06541 ,  H01L2225/06548

Abstract: A semiconductor package includes a first connection structure, a first semiconductor chip on an upper surface of the first connection structure, a first molding layer on the upper surface of the first connection structure and surrounding the first semiconductor chip, a first bond pad on the first semiconductor chip, a first bond insulation layer on the first semiconductor chip and the first molding layer and surrounding the first bond pad, a second bond pad directly contacting the first bond pad, a second bond insulation layer surrounding the second bond pad; and a second semiconductor chip on the second bond pad and the second bond insulation layer.

公开(公告)号：US11552033B2

公开(公告)日：2023-01-10

申请号：US17155657

申请日：2021-01-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuekjae Lee ,  Jongho Lee ,  Jihoon Kim ,  Taehun Kim ,  Sangcheon Park ,  Jinkyeong Seol ,  Sanghoon Lee

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00

Abstract: A semiconductor package includes a first connection structure, a first semiconductor chip on an upper surface of the first connection structure, a first molding layer on the upper surface of the first connection structure and surrounding the first semiconductor chip, a first bond pad on the first semiconductor chip, a first bond insulation layer on the first semiconductor chip and the first molding layer and surrounding the first bond pad, a second bond pad directly contacting the first bond pad, a second bond insulation layer surrounding the second bond pad; and a second semiconductor chip on the second bond pad and the second bond insulation layer.

公开(公告)号：US11824045B2

公开(公告)日：2023-11-21

申请号：US17469954

申请日：2021-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghwan Kim ,  Sangcheon Park

IPC: H01L25/065 ,  H01L23/00 ,  H01L29/06

CPC classification number: H01L25/0657 ,  H01L24/08 ,  H01L29/0684 ,  H01L2224/08146

Abstract: A semiconductor package includes a first, second, third and fourth semiconductor chips sequentially stacked on one another. The second semiconductor chip includes a second substrate and a second substrate recess formed in an edge of a backside surface of the second substrate. The third semiconductor chip includes a third substrate and a first metal residual material provided in a peripheral region of a front surface of the third substrate. When the second semiconductor chip and the third semiconductor chip are bonded to each other such that the front surface of the third substrate and the backside surface of the second substrate face each other, the first metal residual material is located in the second substrate recess. A first bonding pad on the backside surface of the second substrate and a second bonding pad on the front surface of the third substrate are bonded to each other.