公开(公告)号：US11764192B2

公开(公告)日：2023-09-19

申请号：US17861580

申请日：2022-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jihwan Hwang ,  Taehun Kim ,  Jihwan Suh ,  Soyoun Lee ,  Hyuekjae Lee ,  Jiseok Hong

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/06589

Abstract: A semiconductor package and a method of forming the same are provided. The semiconductor package includes one or a plurality of chips on a substrate, bumps disposed below each of the one or plurality of chips, an underfill material layer on the substrate, on a side surface of each of the bumps, and extending to side surfaces of the one or plurality of chips, and a mold layer on the substrate and contacting the underfill material layer. The underfill material layer includes a first side portion, a second side portion on the first side portion and having a slope, steeper than a slope of the first side portion, and a third side portion on the second side portion and having a slope that is less steep than a slope of the second side portion.

公开(公告)号：US11647627B2

公开(公告)日：2023-05-09

申请号：US17168952

申请日：2021-02-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiseok Hong ,  Sangho Lee ,  Seoryong Park ,  Jiyoung Ahn ,  Kiseok Lee ,  Kiseok Lee ,  Yoonyoung Choi ,  Seunguk Han

IPC: H01L27/108

CPC classification number: H01L27/10888 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885

Abstract: An integrated circuit device includes: a substrate including a plurality of active regions; a bit line extending on the substrate in a horizontal direction; a direct contact connected between a first active region selected among the plurality of active regions and the bit line; an inner oxide layer contacting a sidewall of the direct contact; and a carbon-containing oxide layer nonlinearly extending on a sidewall of the bit line in a vertical direction, the carbon-containing oxide layer contacting the sidewall of the bit line.

公开(公告)号：US11251070B2

公开(公告)日：2022-02-15

申请号：US17016537

申请日：2020-09-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiseok Hong ,  Chan-Sic Yoon ,  Ilyoung Moon ,  Jemin Park ,  Kiseok Lee ,  Jung-Hoon Han

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: A method of fabricating a semiconductor device includes providing a substrate, and forming an interlayered insulating layer on the substrate. The method includes forming a preliminary via hole in the interlayered insulating layer. The method includes forming a passivation spacer on an inner side surface of the preliminary via hole. The method includes forming a via hole using the passivation spacer as an etch mask. The method includes forming a conductive via in the via hole. The passivation spacer includes an insulating material different from an insulating material included in the interlayered insulating layer.

公开(公告)号：US20210398569A1

公开(公告)日：2021-12-23

申请号：US17168952

申请日：2021-02-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiseok Hong ,  Sangho Lee ,  Seoryong Park ,  Jiyoung Ahn ,  Kiseok Lee ,  Kiseok Lee ,  Yoonyoung Choi ,  Seunguk Han

IPC: G11C5/06 ,  H01L27/108

Abstract: An integrated circuit device includes: a substrate including a plurality of active regions; a bit line extending on the substrate in a horizontal direction; a direct contact connected between a first active region selected among the plurality of active regions and the bit line; an inner oxide layer contacting a sidewall of the direct contact; and a carbon-containing oxide layer nonlinearly extending on a sidewall of the bit line in a vertical direction, the carbon-containing oxide layer contacting the sidewall of the bit line.

公开(公告)号：US11908797B2

公开(公告)日：2024-02-20

申请号：US17129083

申请日：2020-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiyoung Ahn ,  Seunguk Han ,  Sunghwan Kim ,  Seoryong Park ,  Kiseok Lee ,  Yoonyoung Choi ,  Taehee Han ,  Jiseok Hong

IPC: H01L23/528 ,  H01L29/06 ,  H10B12/00 ,  H01L23/522 ,  H01L21/768 ,  H01L21/764

CPC classification number: H01L23/5283 ,  H01L21/764 ,  H01L21/7682 ,  H01L29/0649 ,  H10B12/482 ,  H10B12/485 ,  H10B12/488 ,  H01L23/5222 ,  H10B12/0335 ,  H10B12/315 ,  H10B12/34

Abstract: An integrated circuit device is provided. The integrated circuit device includes: a bit line on a substrate, the bit line including a lower conductive layer and an upper conductive layer; an insulating capping pattern on the bit line; and a main insulating spacer on a sidewall of the bit line and a sidewall of the insulating capping pattern, the main insulating spacer including an extended portion that is convex toward the upper conductive layer.

公开(公告)号：US11658141B2

公开(公告)日：2023-05-23

申请号：US17680477

申请日：2022-02-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiseok Hong ,  Unbyoung Kang ,  Myungsung Kang ,  Taehun Kim ,  Sangcheon Park ,  Hyuekjae Lee ,  Jihwan Hwang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L21/66 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/08 ,  H01L22/22 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L23/481 ,  H01L2224/05124 ,  H01L2224/05564 ,  H01L2224/05647 ,  H01L2224/06051 ,  H01L2224/08145 ,  H01L2224/2919 ,  H01L2224/29028 ,  H01L2224/32145 ,  H01L2224/9211

Abstract: According to an aspect of the inventive concept, there is provided a die-to-wafer bonding structure including a die having a first test pad, a first bonding pad formed on the first test pad, and a first insulating layer, the first bonding pad penetrates the first insulating layer. The structure may further include a wafer having a second test pad, a second bonding pad formed on the second test pad, and a second insulating layer, the second bonding pad penetrates the second insulating layer. The structure may further include a polymer layer surrounding all side surfaces of the first bonding pad and all side surfaces of the second bonding pad, the polymer layer being arranged between the die and the wafer. Additionally, the wafer and the die may be bonded together.

公开(公告)号：US20220181285A1

公开(公告)日：2022-06-09

申请号：US17680477

申请日：2022-02-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiseok Hong ,  Unbyoung Kang ,  Myungsung Kang ,  Taehun Kim ,  Sangcheon Park ,  Hyuekjae Lee ,  Jihwan Hwang

IPC: H01L23/00 ,  H01L21/66 ,  H01L25/065 ,  H01L25/00

Abstract: According to an aspect of the inventive concept, there is provided a die-to-wafer bonding structure including a die having a first test pad, a first bonding pad formed on the first test pad, and a first insulating layer, the first bonding pad penetrates the first insulating layer. The structure may further include a wafer having a second test pad, a second bonding pad formed on the second test pad, and a second insulating layer, the second bonding pad penetrates the second insulating layer. The structure may further include a polymer layer surrounding all side surfaces of the first bonding pad and all side surfaces of the second bonding pad, the polymer layer being arranged between the die and the wafer. Additionally, the wafer and the die may be bonded together.

公开(公告)号：US20210104482A1

公开(公告)日：2021-04-08

申请号：US16985445

申请日：2020-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiseok Hong ,  Unbyoung Kang ,  Myungsung Kang ,  Taehun Kim ,  Sangcheon Park ,  Hyuekjae Lee ,  Jihwan Hwang

IPC: H01L23/00 ,  H01L21/66 ,  H01L25/00 ,  H01L25/065

Abstract: According to an aspect of the inventive concept, there is provided a die-to-wafer bonding structure including a die having a first test pad, a first bonding pad formed on the first test pad, and a first insulating layer, the first bonding pad penetrates the first insulating layer. The structure may further include a wafer having a second test pad, a second bonding pad formed on the second test pad, and a second insulating layer, the second bonding pad penetrates the second insulating layer. The structure may further include a polymer layer surrounding all side surfaces of the first bonding pad and all side surfaces of the second bonding pad, the polymer layer being arranged between the die and the wafer. Additionally, the wafer and the die may be bonded together.

公开(公告)号：US11721673B2

公开(公告)日：2023-08-08

申请号：US17568558

申请日：2022-01-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuekjae Lee ,  Jihoon Kim ,  Jihwan Suh ,  Soyoun Lee ,  Jiseok Hong ,  Taehun Kim ,  Jihwan Hwang

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/16 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L25/0657 ,  H01L23/16 ,  H01L23/31 ,  H01L23/5386 ,  H01L24/14

Abstract: Provided is a semiconductor package including a semiconductor stack including a first lower chip, a second lower chip, a gap filler disposed between the first lower chip and the second lower chip, and a first upper chip disposed on an upper surface of the first lower chip, an upper surface of the second lower chip, and an upper surface of the gap filler, the first lower chip includes first upper surface pads and a first upper surface dielectric layer, the second lower chip includes second upper surface pads and a second upper surface dielectric layer, the first upper chip includes lower surface pads and a lower surface dielectric layer, and an area of an upper surface of each of the second upper surface pads is greater than an area of a lower surface of each of the lower surface pads.

公开(公告)号：US11557596B2

公开(公告)日：2023-01-17

申请号：US17192086

申请日：2021-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seoryong Park ,  Seunguk Han ,  Jiyoung Ahn ,  Kiseok Lee ,  Yoonyoung Choi ,  Jiseok Hong

IPC: H01L27/11551 ,  H01L27/11519 ,  G11C8/14 ,  H01L27/11578 ,  G11C7/18 ,  H01L27/11565

Abstract: A semiconductor memory device includes a substrate with a cell array region, a first interface region, and a second interface region, the cell array region being provided with active regions, bit lines on the cell array region and the second interface region, dielectric patterns on top surfaces of the bit lines and extending along the top surfaces of the bit lines and further extending onto the first interface region, a device isolation pattern on the substrate, and including a first portion on the cell array region and a second portion on the first interface region, the first portion defining the active regions, the second portion being provided with first recesses, and each first recess being disposed between two adjacent dielectric patterns, and first sacrificial semiconductor patterns disposed on the first interface region and in the first recesses. The first sacrificial semiconductor patterns include polycrystalline silicon.