A method of forming memory cells, high voltage devices and logic devices on fins of a semiconductor substrate's upper surface, and the resulting memory device formed thereby. The memory cells are formed on a pair of the fins, where the floating gate is disposed between the pair of fins, the word line gate wraps around the pair of fins, the control gate is disposed over the floating gate, and the erase gate is disposed over the pair of fins and partially over the floating gate. The high voltage devices include HV gates that wrap around respective fins, and the logic devices include logic gates that are metal and wrap around respective fins.