公开(公告)号：US20240127890A1

公开(公告)日：2024-04-18

申请号：US18536147

申请日：2023-12-11

申请人： Silicon Storage Technology, Inc.

发明人： Hieu Van Tran ,  THUAN VU ,  STANLEY HONG ,  STEPHEN TRINH ,  ANH LY ,  NHAN DO ,  MARK REITEN

IPC分类号： G11C16/08 ,  G11C11/54 ,  G11C16/24

CPC分类号： G11C16/08 ,  G11C11/54 ,  G11C16/24 ,  G11C2216/04

摘要： In one example, a non-volatile memory system, comprises an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain; a plurality of bit lines, each of the plurality of bit lines coupled to the drain or each non-volatile memory cell in a column of non-volatile memory cells; a source line coupled to the source of each non-volatile memory cell; and an adaptive bias decoder for providing a voltage to an erase gate line of the array during an operation, wherein the adaptive bias decoder adjusts the voltage provided to the erase gate line in response to changes in a voltage of the source line.

公开(公告)号：US20240120009A1

公开(公告)日：2024-04-11

申请号：US18530832

申请日：2023-12-06

申请人： Silicon Storage Technology, Inc.

发明人： Hieu Van Tran ,  STEVEN LEMKE ,  NHAN DO ,  Mark REITEN

IPC分类号： G11C16/10 ,  G06F17/16 ,  G06N3/0442 ,  G06N3/063 ,  G11C11/54

CPC分类号： G11C16/10 ,  G06F17/16 ,  G06N3/0442 ,  G06N3/063 ,  G11C11/54 ,  G11C2216/04

摘要： In one example, a method comprises applying a first programming pulse to a terminal of a selected non-volatile memory cell; and applying a second programming pulse to the terminal of the selected non-volatile memory cell, wherein a magnitude of a voltage the second programming pulse is equal to or lower than a magnitude of a voltage of the first programming pulse; wherein the selected non-volatile memory cell is programmed to a target value by the first programming pulse and the second programming pulse.

公开(公告)号：US20220336010A1

公开(公告)日：2022-10-20

申请号：US17856839

申请日：2022-07-01

申请人： Silicon Storage Technology, Inc.

发明人： Hieu Van Tran ,  THUAN VU ,  STEPHEN TRINH ,  STANLEY HONG ,  ANH LY ,  STEVEN LEMKE ,  VIPIN TIWARI ,  NHAN DO

IPC分类号： G11C11/54 ,  G11C16/04 ,  G11C16/08 ,  G11C16/16 ,  G11C16/34 ,  G06N3/063 ,  G11C16/10

摘要： Numerous examples for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed. In one example, an analog neural memory system comprises an array of non-volatile memory cells arranged into rows and columns, each non-volatile memory cell comprising a word line terminal, a bit line terminal, and an erase gate terminal; a plurality of word lines, each word line coupled to word line terminals of a row of non-volatile memory cells; a plurality of bit lines, each bit line coupled to bit line terminals of a column of non-volatile memory cells; and a plurality of erase gate enable transistors, each erase gate enable transistor coupled to erase gate terminals of a word of non-volatile memory cells.

公开(公告)号：US20220101920A1

公开(公告)日：2022-03-31

申请号：US17152696

申请日：2021-01-19

申请人： Silicon Storage Technology, Inc.

发明人： CHUNMING WANG ,  XIAN LIU ,  GUO XIANG SONG ,  LEO XING ,  NHAN DO

IPC分类号： G11C16/04 ,  G11C16/16 ,  H01L29/423 ,  H01L27/11521 ,  H01L27/11556

摘要： A memory device includes a semiconductor substrate, first and second regions in the substrate having a conductivity type different than that of the substrate, with a channel region in the substrate extending between the first and second regions. The channel region is continuous between the first and second regions. A first floating gate is disposed over and insulated from a first portion of the channel region. A second floating gate is disposed over and insulated from a second portion of the channel region. A first coupling gate is disposed over and insulated from the first floating gate. A second coupling gate is disposed over and insulated from the second floating gate. A word line gate is disposed over and insulated from a third portion of the channel region between the first and second channel region portions. An erase gate is disposed over and insulated from the word line gate.

公开(公告)号：US20210209458A1

公开(公告)日：2021-07-08

申请号：US17185725

申请日：2021-02-25

申请人： Silicon Storage Technology, Inc.

发明人： Hieu Van Tran ,  STEVEN LEMKE ,  NHAN DO ,  MARK REITEN

IPC分类号： G06N3/063 ,  G06F17/16

摘要： Numerous embodiments of a precision programming algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.

公开(公告)号：US20200176060A1

公开(公告)日：2020-06-04

申请号：US16783286

申请日：2020-02-06

申请人： Silicon Storage Technology, Inc.

发明人： VIPIN TIWARI ,  NHAN DO ,  HIEU VAN TRAN

IPC分类号： G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  H01L29/423 ,  H01L29/788

摘要： An improved programming technique for non-volatile memory cell arrays, in which memory cells to be programmed with higher programming values are programmed first, and memory cells to be programmed with lower programming values are programmed second. The technique reduces or eliminates the number of previously programmed cells from being adversely incrementally programmed by an adjacent cell being programmed to higher program levels, and reduces the magnitude of adverse incremental programming for most of the memory cells, which is caused by floating gate to floating gate coupling. The memory device includes an array of non-volatile memory cells and a controller configured to identify programming values associated with incoming data, and perform a programming operation in which the incoming data is programmed into at least some of the non-volatile memory cells in a timing order of descending value of the programming values.

公开(公告)号：US20170316823A1

公开(公告)日：2017-11-02

申请号：US15404087

申请日：2017-01-11

申请人： Silicon Storage Technology, Inc. ,  Agency For Science, Technology And Research

发明人： Feng Zhou ,  XIAN LIU ,  NHAN DO ,  HIEU VAN TRAN ,  HUNG QUOC NGUYEN ,  MARK REITEN ,  ZHIXIAN CHEN ,  WANG XINPENG ,  GUO-QIANG LO

IPC分类号： G11C13/00 ,  H01L45/00

CPC分类号： G11C13/0007 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16

摘要： A memory device and method comprising a metal oxide material disposed between and in electrical contact with first and second conductive electrodes, and a voltage source configured to apply a plurality of voltage pulses spaced apart in time across the first and second electrodes. For each one of the voltage pulses, an amplitude of the voltage increases during the voltage pulse.

公开(公告)号：US20240274591A1

公开(公告)日：2024-08-15

申请号：US18110318

申请日：2023-02-15

申请人： Silicon Storage Technology, Inc.

发明人： Jinho KIM ,  CYNTHIA FUNG ,  PARVIZ GHAZAVI ,  JEAN FRANCOIS THIERY ,  CATHERINE DECOBERT ,  GILLES FESTES ,  BRUNO VILLARD ,  YURI TKACHEV ,  XIAN LIU ,  NHAN DO

IPC分类号： H01L27/02 ,  H01L21/38 ,  H01L23/58

CPC分类号： H01L27/0207 ,  H01L21/38 ,  H01L23/585

摘要： A semiconductor device includes a semiconductor substrate, a first module of circuitry formed on the semiconductor substrate, a second module of circuitry formed on the semiconductor substrate, and a communication ring that encircles the first module of circuitry. The communication ring includes an insulation material disposed over the semiconductor substrate, a plurality of electrical connectors disposed over the semiconductor substrate and extending across a width of the communication ring, and a conductive diffusion in the semiconductor substrate that encircles the first module of circuitry.

公开(公告)号：US20220231037A1

公开(公告)日：2022-07-21

申请号：US17716950

申请日：2022-04-08

申请人： Silicon Storage Technology, Inc.

发明人： Serguei Jourba ,  CATHERINE DECOBERT ,  FENG ZHOU ,  JINHO KIM ,  XIAN LIU ,  NHAN DO

IPC分类号： H01L27/11517 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788

摘要： A method of forming a device on a substrate with recessed first/third areas relative to a second area by forming a fin in the second area, forming first source/drain regions (with first channel region therebetween) by first/second implantations, forming second source/drain regions in the third area (defining second channel region therebetween) by the second implantation, forming third source/drain regions in the fin (defining third channel region therebetween) by third implantation, forming a floating gate over a first portion of the first channel region by first polysilicon deposition, forming a control gate over the floating gate by second polysilicon deposition, forming an erase gate over the first source region and a device gate over the second channel region by third polysilicon deposition, and forming a word line gate over a second portion of the first channel region and a logic gate over the third channel region by metal deposition.

公开(公告)号：US20210098477A1

公开(公告)日：2021-04-01

申请号：US17121555

申请日：2020-12-14

申请人： Silicon Storage Technology, Inc.

发明人： Hieu Van Tran ,  STEVEN LEMKE ,  VIPIN TIWARI ,  NHAN DO ,  MARK REITEN

IPC分类号： H01L27/11531 ,  G06N3/08 ,  G11C16/04 ,  H01L29/788

摘要： Numerous embodiments for reading a value stored in a selected memory cell in a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. In one embodiment, an input comprises a set of input bits that result in a series of input pulses applied to a terminal of the selected memory cell, further resulting in a series of output signals that are summed to determine the value stored in the selected memory cell. In another embodiment, an input comprises a set of input bits, where each input bit results in a single pulse or no pulse being applied to a terminal of the selected memory cell, further resulting in a series of output signals which are then weighted according to the binary bit location of the input bit, and where the weighted signals are then summed to determine the value stored in the selected memory cell.