SPLIT-GATE, 2-BIT NON-VOLATILE MEMORY CELL WITH ERASE GATE DISPOSED OVER WORD LINE GATE, AND METHOD OF MAKING SAME

    公开(公告)号:US20220101920A1

    公开(公告)日:2022-03-31

    申请号:US17152696

    申请日:2021-01-19

    Abstract: A memory device includes a semiconductor substrate, first and second regions in the substrate having a conductivity type different than that of the substrate, with a channel region in the substrate extending between the first and second regions. The channel region is continuous between the first and second regions. A first floating gate is disposed over and insulated from a first portion of the channel region. A second floating gate is disposed over and insulated from a second portion of the channel region. A first coupling gate is disposed over and insulated from the first floating gate. A second coupling gate is disposed over and insulated from the second floating gate. A word line gate is disposed over and insulated from a third portion of the channel region between the first and second channel region portions. An erase gate is disposed over and insulated from the word line gate.

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