Invention Application
- Patent Title: Bump Integration with Redistribution Layer
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Application No.: US17492126Application Date: 2021-10-01
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Publication No.: US20220246565A1Publication Date: 2022-08-04
- Inventor: Ting-Li Yang , Po-Hao Tsai , Ching-Wen Hsiao , Hong-Seng Shue , Ming-Da Cheng
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/522 ; H01L23/528 ; H01L21/768

Abstract:
A method of forming a semiconductor device includes: forming an interconnect structure over a substrate; forming a first passivation layer over the interconnect structure; forming a first conductive feature over the first passivation layer and electrically coupled to the interconnect structure; conformally forming a second passivation layer over the first conductive feature and the first passivation layer; forming a dielectric layer over the second passivation layer; and forming a first bump via and a first conductive bump over and electrically coupled to the first conductive feature, where the first bump via is between the first conductive bump and the first conductive feature, where the first bump via extends into the dielectric layer, through the second passivation layer, and contacts the first conductive feature, where the first conductive bump is over the dielectric layer and electrically coupled to the first bump via.
Public/Granted literature
- US12057423B2 Bump integration with redistribution layer Public/Granted day:2024-08-06
Information query
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