公开(公告)号：US12243837B2

公开(公告)日：2025-03-04

申请号：US18231032

申请日：2023-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Li Yang ,  Po-Hao Tsai ,  Ming-Da Cheng ,  Yung-Han Chuang ,  Hsueh-Sheng Wang

IPC: H01L23/00

Abstract: Methods for forming under-bump metallurgy (UBM) structures having different surface profiles and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution line and a second redistribution line over a semiconductor substrate; a first passivation layer over the first redistribution line and the second redistribution line; a first under-bump metallurgy (UBM) structure over and electrically coupled to the first redistribution line, the first UBM structure extending through the first passivation layer, a top surface of the first UBM structure being concave; and a second UBM structure over and electrically coupled to the second redistribution line, the second UBM structure extending through the first passivation layer, a top surface of the second UBM structure being flat or convex.

公开(公告)号：US20220246565A1

公开(公告)日：2022-08-04

申请号：US17492126

申请日：2021-10-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Li Yang ,  Po-Hao Tsai ,  Ching-Wen Hsiao ,  Hong-Seng Shue ,  Ming-Da Cheng

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

Abstract: A method of forming a semiconductor device includes: forming an interconnect structure over a substrate; forming a first passivation layer over the interconnect structure; forming a first conductive feature over the first passivation layer and electrically coupled to the interconnect structure; conformally forming a second passivation layer over the first conductive feature and the first passivation layer; forming a dielectric layer over the second passivation layer; and forming a first bump via and a first conductive bump over and electrically coupled to the first conductive feature, where the first bump via is between the first conductive bump and the first conductive feature, where the first bump via extends into the dielectric layer, through the second passivation layer, and contacts the first conductive feature, where the first conductive bump is over the dielectric layer and electrically coupled to the first bump via.

公开(公告)号：US20220230978A1

公开(公告)日：2022-07-21

申请号：US17326941

申请日：2021-05-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Li Yang ,  Po-Hao Tsai ,  Yi-Wen Wu ,  Sheng-Pin Yang ,  Hao-Chun Liu

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L21/48 ,  H01L49/02

Abstract: A semiconductor device includes a substrate; an interconnect structure over the substrate; a first passivation layer over the interconnect structure; a first conductive pad, a second conductive pad, and a conductive line disposed over the first passivation layer and electrically coupled to conductive features of the interconnect structure; a conformal second passivation layer over and extending along upper surfaces and sidewalls of the first conductive pad, the second conductive pad, and the conductive line; a first conductive bump and a second conductive bump over the first conductive pad and the second conductive pad, respectively, where the first conductive bump and the second conductive bump extend through the conformal second passivation layer and are electrically coupled to the first conductive pad and the second conductive pad, respectively; and a dummy bump over the conductive line, where the dummy bump is separated from the conductive line by the conformal second passivation layer.

公开(公告)号：US20240250019A1

公开(公告)日：2024-07-25

申请号：US18598266

申请日：2024-03-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Li Yang ,  Po-Hao Tsai ,  Ming-Da Cheng ,  Yung-Han Chuang ,  Hsueh-Sheng Wang

IPC: H01L23/522 ,  H01L21/48 ,  H01L23/00 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/486 ,  H01L23/528 ,  H01L24/11 ,  H01L24/14

Abstract: Methods for forming dummy under-bump metallurgy structures and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution line and a second redistribution line over a semiconductor substrate; a first passivation layer over the first redistribution line and the second redistribution line; a second passivation layer over the first passivation layer; a first under-bump metallurgy (UBM) structure over the first redistribution line, the first UBM structure extending through the first passivation layer and the second passivation layer and being electrically coupled to the first redistribution line; and a second UBM structure over the second redistribution line, the second UBM structure extending through the second passivation layer, the second UBM structure being electrically isolated from the second redistribution line by the first passivation layer.

公开(公告)号：US11862588B2

公开(公告)日：2024-01-02

申请号：US17323506

申请日：2021-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Shien Chen ,  Ting-Li Yang ,  Po-Hao Tsai ,  Chien-Chen Li ,  Ming-Da Cheng

IPC: H01L23/31 ,  H01L23/00

CPC classification number: H01L24/05 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/16 ,  H01L2224/0236 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/16225

Abstract: In an embodiment, a device includes: a passivation layer on a semiconductor substrate; a first redistribution line on and extending along the passivation layer; a second redistribution line on and extending along the passivation layer; a first dielectric layer on the first redistribution line, the second redistribution line, and the passivation layer; and an under bump metallization having a bump portion and a first via portion, the bump portion disposed on and extending along the first dielectric layer, the bump portion overlapping the first redistribution line and the second redistribution line, the first via portion extending through the first dielectric layer to be physically and electrically coupled to the first redistribution line.

公开(公告)号：US11851321B2

公开(公告)日：2023-12-26

申请号：US17188933

申请日：2021-03-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ting-Li Yang ,  Kai-Di Wu ,  Ming-Da Cheng ,  Wen-Hsiung Lu ,  Cheng Jen Lin ,  Chin Wei Kang

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81B3/0081 ,  B81C1/0069 ,  B81B2203/019 ,  B81B2203/0127 ,  B81B2203/0353 ,  B81B2207/015 ,  B81C2201/013 ,  B81C2201/0181 ,  B81C2203/032 ,  B81C2203/0735

Abstract: A micro electro mechanical system (MEMS) includes a circuit substrate comprising electronic circuitry, a support substrate having a recess, a bonding layer disposed between the circuit substrate and the support substrate, through holes passing through the circuit substrate to the recess, a first conductive layer disposed on a front side of the circuit substrate, and a second conductive layer disposed on an inner wall of the recess. The first conductive layer extends into the through holes and the second conductive layer extends into the through holes and coupled to the first conductive layer.

公开(公告)号：US20220223548A1

公开(公告)日：2022-07-14

申请号：US17342869

申请日：2021-06-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Li Yang ,  Po-Hao Tsai ,  Ming-Da Cheng ,  Yung-Han Chuang ,  Hsueh-Sheng Wang

IPC: H01L23/00

Abstract: Methods for forming under-bump metallurgy (UBM) structures having different surface profiles and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution line and a second redistribution line over a semiconductor substrate; a first passivation layer over the first redistribution line and the second redistribution line; a first under-bump metallurgy (UBM) structure over and electrically coupled to the first redistribution line, the first UBM structure extending through the first passivation layer, a top surface of the first UBM structure being concave; and a second UBM structure over and electrically coupled to the second redistribution line, the second UBM structure extending through the first passivation layer, a top surface of the second UBM structure being flat or convex.

公开(公告)号：US11855017B2

公开(公告)日：2023-12-26

申请号：US17342869

申请日：2021-06-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Li Yang ,  Po-Hao Tsai ,  Ming-Da Cheng ,  Yung-Han Chuang ,  Hsueh-Sheng Wang

IPC: H01L23/00

CPC classification number: H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/14 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/03462 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/11849 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2924/3841

Abstract: Methods for forming under-bump metallurgy (UBM) structures having different surface profiles and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution line and a second redistribution line over a semiconductor substrate; a first passivation layer over the first redistribution line and the second redistribution line; a first under-bump metallurgy (UBM) structure over and electrically coupled to the first redistribution line, the first UBM structure extending through the first passivation layer, a top surface of the first UBM structure being concave; and a second UBM structure over and electrically coupled to the second redistribution line, the second UBM structure extending through the first passivation layer, a top surface of the second UBM structure being flat or convex.

公开(公告)号：US11557508B2

公开(公告)日：2023-01-17

申请号：US16994091

申请日：2020-08-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Li Yang ,  Wei-Li Huang ,  Sheng-Pin Yang ,  Chi-Cheng Chen ,  Hon-Lin Huang ,  Chin-Yu Ku ,  Chen-Shien Chen

IPC: H01L23/00 ,  H01L23/04 ,  H01L23/522 ,  H01L49/02 ,  H01F41/04 ,  H01F17/00 ,  H01L23/532 ,  H01L21/768

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first conductive line over a substrate. The semiconductor device structure includes a first protection cap over the first conductive line. The semiconductor device structure includes a first photosensitive dielectric layer over the substrate, the first conductive line, and the first protection cap. The semiconductor device structure includes a conductive via structure passing through the first photosensitive dielectric layer and connected to the first protection cap. The semiconductor device structure includes a second conductive line over the conductive via structure and the first photosensitive dielectric layer. The semiconductor device structure includes a second protection cap over the second conductive line. The semiconductor device structure includes a second photosensitive dielectric layer over the first photosensitive dielectric layer, the second conductive line, and the second protection cap.

公开(公告)号：US20240363569A1

公开(公告)日：2024-10-31

申请号：US18763481

申请日：2024-07-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Li Yang ,  Po-Hao Tsai ,  Ching-Wen Hsiao ,  Hong-Seng Shue ,  Ming-Da Cheng

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L24/11 ,  H01L21/76816 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/16 ,  H01L2224/11019 ,  H01L2224/13008 ,  H01L2924/19041

Abstract: A method of forming a semiconductor device includes: forming an interconnect structure over a substrate; forming a first passivation layer over the interconnect structure; forming a first conductive feature over the first passivation layer and electrically coupled to the interconnect structure; conformally forming a second passivation layer over the first conductive feature and the first passivation layer; forming a dielectric layer over the second passivation layer; and forming a first bump via and a first conductive bump over and electrically coupled to the first conductive feature, where the first bump via is between the first conductive bump and the first conductive feature, where the first bump via extends into the dielectric layer, through the second passivation layer, and contacts the first conductive feature, where the first conductive bump is over the dielectric layer and electrically coupled to the first bump via.