公开(公告)号：US20240266304A1

公开(公告)日：2024-08-08

申请号：US18637539

申请日：2024-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao Chun Liu ,  Ching-Wen Hsiao ,  Kuo-Ching Hsu ,  Mirng-Ji Lii

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/58

CPC classification number: H01L23/562 ,  H01L21/563 ,  H01L21/78 ,  H01L23/3185 ,  H01L23/585 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13026 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/35121

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a die structure including a plurality of die regions and a plurality of first seal rings. Each of the plurality of first seal rings surrounds a corresponding die region of the plurality of die regions. The semiconductor device further includes a second seal ring surrounding the plurality of first seal rings and a plurality of connectors bonded to the die structure. Each of the plurality of connectors has an elongated plan-view shape. A long axis of the elongated plan-view shape of each of the plurality of connectors is oriented toward a center of the die structure.

公开(公告)号：US20220278031A1

公开(公告)日：2022-09-01

申请号：US17663970

申请日：2022-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Wen Hsiao ,  Ming-Da Cheng ,  Chih-Wei Lin ,  Chen-Shien Chen ,  Chih-Hua Chen ,  Chen-Cheng Kuo

IPC: H01L23/498 ,  H01L21/683 ,  H01L23/31 ,  H01L25/10

Abstract: A device includes a redistribution line, and a polymer region molded over the redistribution line. The polymer region includes a first flat top surface. A conductive region is disposed in the polymer region and electrically coupled to the redistribution line. The conductive region includes a second flat top surface not higher than the first flat top surface.

公开(公告)号：US20240113080A1

公开(公告)日：2024-04-04

申请号：US18525273

申请日：2023-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Wen Hsiao ,  Chen-Shien Chen ,  Wei Sen Chang ,  Shou-Cheng Hu

IPC: H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/538 ,  H01L23/64

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/538 ,  H01L23/5389 ,  H01L23/64 ,  H01L24/19 ,  H01L24/24 ,  H01L23/50 ,  H01L2924/19105

Abstract: A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device using blocks, e.g., discrete connection blocks, having through vias and/or integrated passive devices formed therein are provided. Embodiments such as those disclosed herein may be utilized in PoP applications. In an embodiment, the semiconductor device includes a die and a connection block encased in a molding compound. Interconnection layers may be formed on surfaces of the die, the connection block and the molding compound. One or more dies and/or packages may be attached to the interconnection layers.

公开(公告)号：US11855045B2

公开(公告)日：2023-12-26

申请号：US17567435

申请日：2022-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Wen Hsiao ,  Chen-Shien Chen ,  Wei Sen Chang ,  Shou-Cheng Hu

IPC: H01L29/00 ,  H01L25/065 ,  H01L23/64 ,  H01L23/00 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/522 ,  H01L21/683 ,  H01L23/31 ,  H01L23/48 ,  H01L23/528 ,  H01L23/50

CPC classification number: H01L25/0657 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/56 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/481 ,  H01L23/528 ,  H01L23/5222 ,  H01L23/538 ,  H01L23/5389 ,  H01L23/64 ,  H01L24/19 ,  H01L24/24 ,  H01L23/50 ,  H01L2221/68327 ,  H01L2221/68359 ,  H01L2224/0231 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/11002 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24195 ,  H01L2224/2518 ,  H01L2224/73267 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/181 ,  H01L2924/00

Abstract: A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device using blocks, e.g., discrete connection blocks, having through vias and/or integrated passive devices formed therein are provided. Embodiments such as those disclosed herein may be utilized in PoP applications. In an embodiment, the semiconductor device includes a die and a connection block encased in a molding compound. Interconnection layers may be formed on surfaces of the die, the connection block and the molding compound. One or more dies and/or packages may be attached to the interconnection layers.

公开(公告)号：US11488878B2

公开(公告)日：2022-11-01

申请号：US17215135

申请日：2021-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hua Chen ,  Chen-Shien Chen ,  Ching-Wen Hsiao

IPC: H01L21/66 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L23/522 ,  H01L23/31 ,  H01L23/528 ,  H01L25/18

Abstract: Embodiments of mechanisms for testing a die package with multiple packaged dies on a package substrate use an interconnect substrate to provide electrical connections between dies and the package substrate and to provide probing structures (or pads). Testing structures, including daisy-chain structures, with metal lines to connect bonding structures connected to signals, power source, and/or grounding structures are connected to probing structures on the interconnect substrate. The testing structures enable determining the quality of bonding and/or functionalities of packaged dies bonded. After electrical testing is completed, the metal lines connecting the probing structures and the bonding structures are severed to allow proper function of devices in the die package. The mechanisms for forming test structures with probing pads on interconnect substrate and severing connecting metal lines after testing could reduce manufacturing cost.

公开(公告)号：US20220122944A1

公开(公告)日：2022-04-21

申请号：US17567435

申请日：2022-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Wen Hsiao ,  Chen-Shien Chen ,  Wei Sen Chang ,  Shou-Cheng Hu

IPC: H01L25/065 ,  H01L23/64 ,  H01L23/00 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/522 ,  H01L21/683 ,  H01L23/31 ,  H01L23/48 ,  H01L23/528

Abstract: A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device using blocks, e.g., discrete connection blocks, having through vias and/or integrated passive devices formed therein are provided. Embodiments such as those disclosed herein may be utilized in PoP applications. In an embodiment, the semiconductor device includes a die and a connection block encased in a molding compound. Interconnection layers may be formed on surfaces of the die, the connection block and the molding compound. One or more dies and/or packages may be attached to the interconnection layers.

公开(公告)号：US20200328169A1

公开(公告)日：2020-10-15

申请号：US16915780

申请日：2020-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Yen-Chang Hu ,  Ching-Wen Hsiao ,  Mirng-Ji Lii ,  Chung-Shi Liu ,  Chien Ling Hwang ,  Chih-Wei Lin ,  Chen-Shien Chen

IPC: H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L21/56 ,  H01L23/538

Abstract: A method embodiment includes forming a sacrificial film layer over a top surface of a die, the die having a contact pad at the top surface. The die is attached to a carrier, and a molding compound is formed over the die and the sacrificial film layer. The molding compound extends along sidewalls of the die. The sacrificial film layer is exposed. The contact pad is exposed by removing at least a portion of the sacrificial film layer. A first polymer layer is formed over the die, and a redistribution layer (RDL) is formed over the die and electrically connects to the contact pad.

公开(公告)号：US20200243410A1

公开(公告)日：2020-07-30

申请号：US16852569

申请日：2020-04-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Yun Tu ,  Ching-Wen Hsiao ,  Sheng-Yu Wu ,  Ching-Hui Chen

IPC: H01L23/31 ,  H01L21/66 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56 ,  H01L21/768 ,  H01L21/78 ,  H01L23/498 ,  H01L21/683 ,  H01L25/10

Abstract: Conductive structures and the redistribution circuit structures are disclosed. One of the conductive structures includes a first conductive layer and a second conductive layer. The first conductive layer is disposed in a lower portion of a dielectric layer, and the first conductive layer includes an upper surface with a protrusion at an edge. The second conductive layer is disposed in an upper portion of the dielectric layer and electrically connected to the first conductive layer. An upper surface of the second conductive layer is conformal with the upper surface of the first conductive layer.

公开(公告)号：US20240363569A1

公开(公告)日：2024-10-31

申请号：US18763481

申请日：2024-07-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Li Yang ,  Po-Hao Tsai ,  Ching-Wen Hsiao ,  Hong-Seng Shue ,  Ming-Da Cheng

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L24/11 ,  H01L21/76816 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/16 ,  H01L2224/11019 ,  H01L2224/13008 ,  H01L2924/19041

Abstract: A method of forming a semiconductor device includes: forming an interconnect structure over a substrate; forming a first passivation layer over the interconnect structure; forming a first conductive feature over the first passivation layer and electrically coupled to the interconnect structure; conformally forming a second passivation layer over the first conductive feature and the first passivation layer; forming a dielectric layer over the second passivation layer; and forming a first bump via and a first conductive bump over and electrically coupled to the first conductive feature, where the first bump via is between the first conductive bump and the first conductive feature, where the first bump via extends into the dielectric layer, through the second passivation layer, and contacts the first conductive feature, where the first conductive bump is over the dielectric layer and electrically coupled to the first bump via.

公开(公告)号：US12057423B2

公开(公告)日：2024-08-06

申请号：US17492126

申请日：2021-10-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Li Yang ,  Po-Hao Tsai ,  Ching-Wen Hsiao ,  Hong-Seng Shue ,  Ming-Da Cheng

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L24/11 ,  H01L21/76816 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/16 ,  H01L2224/11019 ,  H01L2224/13008 ,  H01L2924/19041

Abstract: A method of forming a semiconductor device includes: forming an interconnect structure over a substrate; forming a first passivation layer over the interconnect structure; forming a first conductive feature over the first passivation layer and electrically coupled to the interconnect structure; conformally forming a second passivation layer over the first conductive feature and the first passivation layer; forming a dielectric layer over the second passivation layer; and forming a first bump via and a first conductive bump over and electrically coupled to the first conductive feature, where the first bump via is between the first conductive bump and the first conductive feature, where the first bump via extends into the dielectric layer, through the second passivation layer, and contacts the first conductive feature, where the first conductive bump is over the dielectric layer and electrically coupled to the first bump via.