公开(公告)号：US20170062334A1

公开(公告)日：2017-03-02

申请号：US15350372

申请日：2016-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Chun-Yi Yang ,  Chih-Hao Lin ,  Hong-Seng Shue ,  Ruei-Hung Jang

IPC: H01L23/525 ,  H01L23/00

CPC classification number: H01L23/5256 ,  H01L23/5258 ,  H01L24/05 ,  H01L24/45 ,  H01L2224/04042 ,  H01L2224/05571 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2224/45099

Abstract: The present disclosure relates to a semiconductor device. A fuse layer is arranged within a first dielectric layer. A bond pad is arranged on the first dielectric layer. A second dielectric layer is arranged along sidewall and upper surfaces of the bond pad. A passivation layer is arranged over the first and second dielectric layers, and the passivation layer having a bond pad opening overlying the bond pad and a fuse opening overlying the fuse layer. The bond pad has a bottom surface that is co-planar with a bottom surface of the passivation layer.

Abstract translation: 本公开涉及半导体器件。 熔丝层布置在第一介电层内。 接合焊盘设置在第一介电层上。 第二电介质层沿接合焊盘的侧壁和上表面布置。 钝化层布置在第一和第二电介质层上，并且钝化层具有覆盖接合焊盘的接合焊盘开口和覆盖熔丝层的保险丝开口。 接合焊盘具有与钝化层的底表面共面的底表面。

公开(公告)号：US20150325642A1

公开(公告)日：2015-11-12

申请号：US14806854

申请日：2015-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Shou-Wei Lee ,  Shao-Chi Yu ,  Hong-Seng Shue ,  Kun-Ming Huang ,  Po-Tao Chu

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/308 ,  H01L21/225 ,  H01L29/10 ,  H01L21/762 ,  H01L21/324

CPC classification number: H01L29/0634 ,  H01L21/2254 ,  H01L21/2257 ,  H01L21/308 ,  H01L21/324 ,  H01L21/761 ,  H01L21/76224 ,  H01L29/0692 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7811

Abstract: A high-voltage super junction device is disclosed. The device includes a semiconductor substrate region having a first conductivity type and having neighboring trenches disposed therein. The neighboring trenches each have trench sidewalls and a trench bottom surface. A region having a second conductivity type is disposed in or adjacent to a trench and meets the semiconductor substrate region at a p-n junction. A gate electrode is formed on the semiconductor substrate region and electrically is electrically isolated from the semiconductor substrate region by a gate dielectric. A body region having the second conductivity type is disposed on opposite sides of the gate electrode near a surface of the semiconductor substrate. A source region having the first conductivity type is disposed within in the body region on opposite sides of the gate electrode near the surface of the semiconductor substrate.

公开(公告)号：US09093520B2

公开(公告)日：2015-07-28

申请号：US14011991

申请日：2013-08-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Shou-Wei Lee ,  Shao-Chi Yu ,  Hong-Seng Shue ,  Kun-Ming Huang ,  Po-Tao Chu

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L29/0634 ,  H01L21/2254 ,  H01L21/2257 ,  H01L21/308 ,  H01L21/324 ,  H01L21/761 ,  H01L21/76224 ,  H01L29/0692 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7811

Abstract: A high-voltage super junction device is disclosed. The device includes a semiconductor substrate region having a first conductivity type and having neighboring trenches disposed therein. The neighboring trenches each have trench sidewalls and a trench bottom surface. A region having a second conductivity type is disposed in or adjacent to a trench and meets the semiconductor substrate region at a p-n junction. A gate electrode is formed on the semiconductor substrate region and is electrically isolated from the semiconductor substrate region by a gate dielectric. A body region having the second conductivity type is disposed on opposite sides of the gate electrode near a surface of the semiconductor substrate. A source region having the first conductivity type is disposed within in the body region on opposite sides of the gate electrode near the surface of the semiconductor substrate.

Abstract translation: 公开了一种高压超导装置。 该器件包括具有第一导电类型并且其中设置有相邻沟槽的半导体衬底区域。 相邻的沟槽各具有沟槽侧壁和沟槽底面。 具有第二导电类型的区域设置在沟槽中或邻近沟槽，并在p-n结处与半导体衬底区域相遇。 栅极电极形成在半导体衬底区域上，并通过栅极电介质与半导体衬底区域电隔离。 具有第二导电类型的主体区域设置在靠近半导体衬底的表面的栅电极的相对侧上。 具有第一导电类型的源极区域设置在靠近半导体衬底的表面的栅电极的相对侧的体区内。

公开(公告)号：US20240379584A1

公开(公告)日：2024-11-14

申请号：US18780104

申请日：2024-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsiang Tseng ,  Yu-Feng Chen ,  Cheng Jen Lin ,  Wen-Hsiung Lu ,  Ming-Da Cheng ,  Kuo-Ching Hsu ,  Hong-Seng Shue ,  Ming-Hong Cha ,  Chao-Yi Wang ,  Mirng-Ji Lii

IPC: H01L23/58 ,  H01L21/02 ,  H01L21/48 ,  H01L23/31 ,  H01L23/522 ,  H01L23/532

Abstract: A semiconductor package includes a first die having a first substrate, an interconnect structure overlying the first substrate and having multiple metal layers with vias connecting the multiple metal layers, a seal ring structure overlying the first substrate and along a periphery of the first substrate, the seal ring structure having multiple metal layers with vias connecting the multiple metal layers, the seal ring structure having a topmost metal layer, the topmost metal layer being the metal layer of the seal ring structure that is furthest from the first substrate, the topmost metal layer of the seal ring structure having an inner metal structure and an outer metal structure, and a polymer layer over the seal ring structure, the polymer layer having an outermost edge that is over and aligned with a top surface of the outer metal structure of the seal ring structure.

公开(公告)号：US20240363457A1

公开(公告)日：2024-10-31

申请号：US18767481

申请日：2024-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Hung Chen ,  Hong-Seng Shue ,  Po-Hao Tsai ,  Mirng-Ji Lii

IPC: H01L23/10 ,  H01L21/50 ,  H01L21/762 ,  H01L23/522

CPC classification number: H01L23/10 ,  H01L21/50 ,  H01L21/76297 ,  H01L23/5226

Abstract: A method includes forming a plurality of dielectric layers, forming a lower portion of a seal ring including a plurality of metal layers, each extending into one of the plurality of dielectric layers, depositing a first passivation layer over the plurality of dielectric layers, forming an opening in the first passivation layer, forming a via ring in the opening and physically contacting the lower portion of the seal ring, and forming a metal ring over the first passivation layer and joined to the via ring. The via ring and the metal ring form an upper portion of the seal ring. The metal ring includes an edge portion having a zigzag pattern. The method further includes forming a second passivation layer on the metal ring, and performing a singulation process to form a device die, with the seal ring being proximate edges of the device die.

公开(公告)号：US12087648B2

公开(公告)日：2024-09-10

申请号：US17659048

申请日：2022-04-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Hung Chen ,  Hong-Seng Shue ,  Po-Hao Tsai ,  Mirng-Ji Lii

IPC: H01L23/10 ,  H01L21/50 ,  H01L21/762 ,  H01L23/522

CPC classification number: H01L23/10 ,  H01L21/50 ,  H01L21/76297 ,  H01L23/5226

Abstract: A method includes forming a plurality of dielectric layers, forming a lower portion of a seal ring including a plurality of metal layers, each extending into one of the plurality of dielectric layers, depositing a first passivation layer over the plurality of dielectric layers, forming an opening in the first passivation layer, forming a via ring in the opening and physically contacting the lower portion of the seal ring, and forming a metal ring over the first passivation layer and joined to the via ring. The via ring and the metal ring form an upper portion of the seal ring. The metal ring includes an edge portion having a zigzag pattern. The method further includes forming a second passivation layer on the metal ring, and performing a singulation process to form a device die, with the seal ring being proximate edges of the device die.

公开(公告)号：US08975153B2

公开(公告)日：2015-03-10

申请号：US13866102

申请日：2013-04-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Hong-Seng Shue ,  Kun-Ming Huang ,  Tzu-Cheng Chen ,  Ming-Che Yang ,  Po-Tao Chu

IPC: H01L21/02 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L29/7802 ,  H01L21/823425 ,  H01L21/823481 ,  H01L21/8238 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0634

Abstract: A method for forming a semiconductor device includes forming a hard mask layer over a substrate comprising a semiconductor material of a first conductivity type, and forming a plurality of trenches in the hard mask layer and extending into the substrate. Each trench has at least one side wall and a bottom wall. The method further includes forming at least one barrier insulator layer along the at least one side wall and over the bottom wall of each trench, removing the at least one barrier insulator layer over the bottom wall of each trench, and filling the plurality of trenches with a semiconductor material of a second conductivity type.

Abstract translation: 一种形成半导体器件的方法包括在包括第一导电类型的半导体材料的衬底上形成硬掩模层，并且在硬掩模层中形成并延伸到衬底中的多个沟槽。 每个沟槽具有至少一个侧壁和底壁。 该方法还包括沿着每个沟槽的至少一个侧壁和底壁上形成至少一个阻挡绝缘体层，在每个沟槽的底壁上去除至少一个阻挡绝缘体层，并且将多个沟槽填充到 第二导电类型的半导体材料。

公开(公告)号：US20240363569A1

公开(公告)日：2024-10-31

申请号：US18763481

申请日：2024-07-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Li Yang ,  Po-Hao Tsai ,  Ching-Wen Hsiao ,  Hong-Seng Shue ,  Ming-Da Cheng

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L24/11 ,  H01L21/76816 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/16 ,  H01L2224/11019 ,  H01L2224/13008 ,  H01L2924/19041

Abstract: A method of forming a semiconductor device includes: forming an interconnect structure over a substrate; forming a first passivation layer over the interconnect structure; forming a first conductive feature over the first passivation layer and electrically coupled to the interconnect structure; conformally forming a second passivation layer over the first conductive feature and the first passivation layer; forming a dielectric layer over the second passivation layer; and forming a first bump via and a first conductive bump over and electrically coupled to the first conductive feature, where the first bump via is between the first conductive bump and the first conductive feature, where the first bump via extends into the dielectric layer, through the second passivation layer, and contacts the first conductive feature, where the first conductive bump is over the dielectric layer and electrically coupled to the first bump via.

公开(公告)号：US12057423B2

公开(公告)日：2024-08-06

申请号：US17492126

申请日：2021-10-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Li Yang ,  Po-Hao Tsai ,  Ching-Wen Hsiao ,  Hong-Seng Shue ,  Ming-Da Cheng

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L24/11 ,  H01L21/76816 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/16 ,  H01L2224/11019 ,  H01L2224/13008 ,  H01L2924/19041

Abstract: A method of forming a semiconductor device includes: forming an interconnect structure over a substrate; forming a first passivation layer over the interconnect structure; forming a first conductive feature over the first passivation layer and electrically coupled to the interconnect structure; conformally forming a second passivation layer over the first conductive feature and the first passivation layer; forming a dielectric layer over the second passivation layer; and forming a first bump via and a first conductive bump over and electrically coupled to the first conductive feature, where the first bump via is between the first conductive bump and the first conductive feature, where the first bump via extends into the dielectric layer, through the second passivation layer, and contacts the first conductive feature, where the first conductive bump is over the dielectric layer and electrically coupled to the first bump via.

公开(公告)号：US11848270B2

公开(公告)日：2023-12-19

申请号：US16422988

申请日：2019-05-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hong-Seng Shue ,  Sheng-Han Tsai ,  Kuo-Chin Chang ,  Mirng-Ji Lii ,  Kuo-Ching Hsu

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L24/08 ,  H01L24/09 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/023 ,  H01L2224/0224 ,  H01L2224/0225 ,  H01L2224/0231 ,  H01L2224/0233 ,  H01L2224/02235 ,  H01L2224/02245 ,  H01L2224/02255 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/081 ,  H01L2224/0805 ,  H01L2224/08052 ,  H01L2224/08113 ,  H01L2224/16104

Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes a redistribution layer over the substrate. The chip structure includes a bonding pad over the redistribution layer. The chip structure includes a shielding pad over the redistribution layer and surrounding the bonding pad. The chip structure includes an insulating layer over the redistribution layer and the shielding pad. The chip structure includes a bump over the bonding pad and the insulating layer. A sidewall of the bump is over the shielding pad.