- 专利标题: TECHNOLOGIES FOR PEROVSKITE TRANSISTORS
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申请号: US17956296申请日: 2022-09-29
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公开(公告)号: US20240113212A1公开(公告)日: 2024-04-04
- 发明人: Ian Alexander Young , Dmitri Evgenievich Nikonov , Marko Radosavljevic , Matthew V. Metz , John J. Plombon , Raseong Kim , Kevin P. O'Brien , Scott B. Clendenning , Tristan A. Tronic , Dominique A. Adams , Carly Rogan , Hai Li , Arnab Sen Gupta , Gauri Auluck , I-Cheng Tung , Brandon Holybee , Rachel A. Steinhardt , Punyashloka Debashis
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 主分类号: H01L29/775
- IPC分类号: H01L29/775 ; H01L21/02 ; H01L21/465 ; H01L29/06 ; H01L29/24 ; H01L29/423 ; H01L29/49 ; H01L29/66
摘要:
Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a perovskite stack is grown on a buffer layer as part of manufacturing a transistor. The perovskite stack includes one or more doped semiconductor layers alternating with other lattice-matched layers, such as undoped semiconductor layers. Growing the doped semiconductor layers on lattice-matched layers can improve the quality of the doped semiconductor layers. The lattice-matched layers can be preferentially etched away, leaving the doped semiconductor layers as fins for a ribbon FET. In another embodiment, an interlayer can be deposited on top of a semiconductor layer, and a ferroelectric layer can be deposited on the interlayer. The interlayer can bridge a gap in lattice parameters between the semiconductor layer and the ferroelectric layer.
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