公开(公告)号：US20240429301A1

公开(公告)日：2024-12-26

申请号：US18341467

申请日：2023-06-26

Applicant: Intel Corporation

Inventor： Rachel A. Steinhardt ,  Dmitri Evgenievich Nikonov ,  Kevin P. O'Brien ,  John J. Plombon ,  Tristan A. Tronic ,  Ian Alexander Young ,  Matthew V. Metz ,  Marko Radosavljevic ,  Carly Rogan ,  Brandon Holybee ,  Raseong Kim ,  Punyashloka Debashis ,  Dominique A. Adams ,  I-Cheng Tung ,  Arnab Sen Gupta ,  Gauri Auluck ,  Scott B. Clendenning ,  Pratyush P. Buragohain

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786

Abstract: A transistor device may be formed with a doped perovskite material as a channel region. The doped perovskite material may be formed via an epitaxial growth process from a seed layer, and the channel regions of the transistor device may be formed from lateral overgrowth from the epitaxial growth process.

公开(公告)号：US20240114692A1

公开(公告)日：2024-04-04

申请号：US17958395

申请日：2022-10-01

Applicant: Intel Corporation

Inventor： Nazila Haratipour ,  Uygar E. Avci ,  Vachan Kumar ,  Hai Li ,  Yu-Ching Liao ,  Ian Alexander Young

IPC: H01L27/11502 ,  G11C11/22 ,  H01L27/108 ,  H01L29/94

CPC classification number: H01L27/11502 ,  G11C11/221 ,  G11C11/223 ,  H01L27/1087 ,  H01L29/945

Abstract: Inverted pillar capacitors that have a U-shaped insulating layer are oriented with the U-shaped opening of the insulating layer opening toward the surface of the substrate on which the inverted pillar capacitors are formed. The bottom electrodes of adjacent inverted pillar capacitors are isolated from each other by the insulating layers of the adjacent electrodes and the top electrode that fills the volume between the electrodes. By avoiding the need to isolate adjacent bottom electrodes by an isolation dielectric region, inverted pillar capacitors can provide for a greater capacitor density relative to non-inverted pillar capacitors. The insulating layer in inverted pillar capacitors can comprise a ferroelectric material or an antiferroelectric material. The inverted pillar capacitor can be used in memory circuits (e.g., DRAMs) or non-memory applications.

公开(公告)号：US20240105822A1

公开(公告)日：2024-03-28

申请号：US17953648

申请日：2022-09-27

Applicant: Intel Corporation

Inventor： Kevin P. O'Brien ,  Brandon Holybee ,  Carly Rogan ,  Dmitri Evgenievich Nikonov ,  Punyashloka Debashis ,  Rachel A. Steinhardt ,  Tristan A. Tronic ,  Ian Alexander Young ,  Marko Radosavljevic ,  John J. Plombon

IPC: H01L29/775 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/775 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66969

Abstract: A transistor device may include a first perovskite gate material, a first perovskite ferroelectric material on the first gate material, a first perovskite semiconductor material on the first ferroelectric material, a second perovskite ferroelectric material on the first semiconductor material, a second perovskite gate material on the second ferroelectric material, a third perovskite ferroelectric material on the second gate material, a second perovskite semiconductor material on the third ferroelectric material, a fourth perovskite ferroelectric material on the second semiconductor material, a third perovskite gate material on the fourth ferroelectric material, a first source/drain metal adjacent a first side of each of the first semiconductor material and the second semiconductor material, a second source/drain metal adjacent a second side opposite the first side of each of the first semiconductor material and the second semiconductor material, and dielectric materials between the source/drain metals and the gate materials.

公开(公告)号：US20230200079A1

公开(公告)日：2023-06-22

申请号：US17555207

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Tanay A. Gosavi ,  Uygar E. Avci ,  Sou-Chi Chang ,  Hai Li ,  Dmitri Evgenievich Nikonov ,  Kaan Oguz ,  Ashish Verma Penumatcha ,  John J. Plombon ,  Ian Alexander Young

IPC: H01L27/11514 ,  H01L49/02 ,  H01L29/51

CPC classification number: H01L27/11514 ,  H01L28/65 ,  H01L29/516

Abstract: A first type of ferroelectric capacitor comprises electrodes and an insulating layer comprising ferroelectric oxides. In some embodiments, the electrodes and the insulating layer comprise perovskite ferroelectric oxides. A second type of ferroelectric capacitor comprises a ferroelectric insulating layer comprising certain monochalcogenides. Both types of ferroelectric capacitors can have a coercive voltage that is less than one volt. Such capacitors are attractive for use in low-voltage non-volatile embedded memories for next-generation semiconductor manufacturing technologies.

公开(公告)号：US20230058938A1

公开(公告)日：2023-02-23

申请号：US17409483

申请日：2021-08-23

Applicant: Intel Corporation

Inventor： Punyashloka Debashis ,  Dmitri Evgenievich Nikonov ,  Hai Li ,  Chia-Ching Lin ,  Raseong Kim ,  Tanay A. Gosavi ,  Ashish Verma Penumatcha ,  Uygar E. Avci ,  Marko Radosavljevic ,  Ian Alexander Young

IPC: G11C11/22 ,  H01L27/1159

Abstract: A pbit device, in one embodiment, includes a first field-effect transistor (FET) that includes a source region, a drain region, a source electrode on the source region, a drain electrode on the drain region, a channel region between the source and drain regions, a dielectric layer on a surface over the channel region, an electrode layer above the dielectric layer, and a ferroelectric (FE) material layer between the dielectric layer and the electrode layer. The pbit device also includes a second FET comprising a source electrode, a drain electrode, and a gate electrode. The drain electrode of the second FET is connected to the drain electrode of the first FET.

公开(公告)号：US20250008852A1

公开(公告)日：2025-01-02

申请号：US18346212

申请日：2023-07-01

Applicant: Intel Corporation

Inventor： Punyashloka Debashis ,  Dominique A. Adams ,  Gauri Auluck ,  Scott B. Clendenning ,  Arnab Sen Gupta ,  Brandon Holybee ,  Raseong Kim ,  Matthew V. Metz ,  Kevin P. O'Brien ,  John J. Plombon ,  Marko Radosavljevic ,  Carly Rogan ,  Hojoon Ryu ,  Rachel A. Steinhardt ,  Tristan A. Tronic ,  I-Cheng Tung ,  Ian Alexander Young ,  Dmitri Evgenievich Nikonov

IPC: H10N70/00 ,  H10B63/00 ,  H10B99/00

Abstract: A two-terminal ferroelectric perovskite diode comprises a region of ferroelectric perovskite material positioned adjacent to a region of n-type doped perovskite semiconductor material. Asserting a positive voltage across the diode can cause the polarization of the ferroelectric perovskite material to be set in a first direction that causes the diode to be placed in a low resistance state due to the formation of an accumulation region in the perovskite semiconductor material at the ferroelectric perovskite-perovskite semiconductor boundary. Asserting a negative voltage across the diode can cause the polarization of the ferroelectric perovskite material to be set in a second direction that causes the diode to be placed in a high resistance state due to the formation of a depletion region in the perovskite semiconductor material at the ferroelectric perovskite-perovskite semiconductor material. These non-volatile low and high resistance states enable the diode to be used as a non-volatile memory element.

公开(公告)号：US20240224814A1

公开(公告)日：2024-07-04

申请号：US18148240

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Punyashloka Debashis ,  Dmitri Evgenievich Nikonov ,  Ian Alexander Young ,  Hai Li

IPC: H10N50/85 ,  G11C11/16 ,  H01F10/32 ,  H03K19/18 ,  H10N52/80

CPC classification number: H10N50/85 ,  G11C11/161 ,  H01F10/3286 ,  H03K19/18 ,  H10N52/80

Abstract: Valleytronic magnetoelectric spin-orbit (MESO) logic devices comprise a charge-to-spin conversion input module that comprises a magnetoelectric capacitor. The input module converts a differential input voltage into a magnetization orientation of a ferromagnet possessing in-plane anisotropy (IPA) through exchange coupling between the IPA ferromagnet and the magnetoelectric layer of the capacitor. The magnetization orientation of the IPA ferromagnet can represent the logic state of the valleytronic MESO device. A spin-to-charge conversion output module comprises a ferromagnet possessing perpendicular magnetic anisotropy (PMA) and a 2D valleytronic material. The IMA and PMA ferromagnets are chirally-coupled through Dzaloshinskii-Moriya interaction, which causes the perpendicular magnetic orientation of the PMA ferromagnet to switch with the in-plane magnetization orientation of the IPA ferromagnet. The logic state of the device is read through injection of spin-polarized current from the PMA ferromagnet into the 2D valleytronic layer, which converts the injected spin-polarized current into a differential output current.

公开(公告)号：US20240120415A1

公开(公告)日：2024-04-11

申请号：US17958362

申请日：2022-10-01

Applicant: Intel Corporation

Inventor： Scott B. Clendenning ,  Sudarat Lee ,  Kevin P. O'Brien ,  Rachel A. Steinhardt ,  John J. Plombon ,  Arnab Sen Gupta ,  Charles C. Mokhtarzadeh ,  Gauri Auluck ,  Tristan A. Tronic ,  Brandon Holybee ,  Matthew V. Metz ,  Dmitri Evgenievich Nikonov ,  Ian Alexander Young

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/778 ,  H01L21/02197 ,  H01L29/0665 ,  H01L29/66795 ,  H01L29/78391

Abstract: Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a perovskite stack is grown on a buffer layer as part of manufacturing a transistor. The perovskite stack includes one or more doped semiconductor layers alternating with other lattice-matched layers. Growing the doped semiconductor layers on lattice-matched layers can improve the quality of the doped semiconductor layers. The lattice-matched layers can be etched away, leaving the doped semiconductor layers as fins for a ribbon FET. A ferroelectric layer can be conformally grown on the fins, creating a high-quality ferroelectric layer above and below the fins. A gate can then be grown on the ferroelectric layer.

公开(公告)号：US20230320230A1

公开(公告)日：2023-10-05

申请号：US17709074

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Punyashloka Debashis ,  Hai Li ,  Chia-Ching Lin ,  Dmitri Evgenievich Nikonov ,  Ian Alexander Young

IPC: H01L43/10 ,  H01L43/04 ,  H01L43/06 ,  H01L43/14 ,  H01L27/22

CPC classification number: H01L43/10 ,  H01L43/04 ,  H01L43/065 ,  H01L43/14 ,  H01L27/228 ,  H03K19/18

Abstract: In one embodiment, an integrated circuit die includes: a first layer comprising a magnetoelectric material; a second layer comprising a monolayer transition metal dichalcogenide (TMD); a magnet between the first layer and the second layer, wherein the magnet has perpendicular magnetic anisotropy; a first conductive trace coupled to the first layer; and a second conductive trace coupled to the magnet.

公开(公告)号：US20230317847A1

公开(公告)日：2023-10-05

申请号：US17711665

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Hai Li ,  Ian Alexander Young ,  Dmitri Evgenievich Nikonov ,  Julien Sebot ,  Raseong Kim ,  Chia-Ching Lin ,  Punyashloka Debashis

IPC: H01L29/78 ,  H01L43/10

CPC classification number: H01L29/78391 ,  H01L43/10

Abstract: Technologies for majority gates are disclosed. In one embodiment, a ferroelectric layer has three inputs and an output adjacent a surface of the ferroelectric. When a voltage is applied to each input, the inputs and a ground plane below the ferroelectric layer form a capacitor. The ferroelectric layer becomes polarized based on the applied voltages at the inputs. The portion of the ferroelectric layer near the output becomes polarized in the direction of polarization of the majority of the inputs. The output voltage then reflects the majority voltage of the inputs.