公开(公告)号：US20240105810A1

公开(公告)日：2024-03-28

申请号：US17952161

申请日：2022-09-23

申请人： Intel Corporation

发明人： Rachel A. Steinhardt ,  Ian Alexander Young ,  Dmitri Evgenievich Nikonov ,  Marko Radosavljevic ,  Matthew V. Metz ,  John J. Plombon ,  Raseong Kim ,  Kevin P. O'Brien ,  Scott B. Clendenning ,  Tristan A. Tronic ,  Dominique A. Adams ,  Carly Rogan ,  Arnab Sen Gupta ,  Brandon Holybee ,  Punyashloka Debashis ,  I-Cheng Tung ,  Gauri Auluck

IPC分类号： H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/516 ,  H01L29/6684 ,  H01L29/66969 ,  H01L29/7831

摘要： In one embodiment, transistor device includes a first source or drain material on a substrate, a semiconductor material on the first source or drain material, a second source or drain material on the semiconductor material, a dielectric layer on the substrate and adjacent the first source or drain material, a ferroelectric (FE) material on the dielectric layer and adjacent the semiconductor material, and a gate material on or adjacent to the FE material. The FE material may be a perovskite material and may have a lattice parameter that is less than a lattice parameter of the semiconductor material.

公开(公告)号：US20240105822A1

公开(公告)日：2024-03-28

申请号：US17953648

申请日：2022-09-27

申请人： Intel Corporation

发明人： Kevin P. O'Brien ,  Brandon Holybee ,  Carly Rogan ,  Dmitri Evgenievich Nikonov ,  Punyashloka Debashis ,  Rachel A. Steinhardt ,  Tristan A. Tronic ,  Ian Alexander Young ,  Marko Radosavljevic ,  John J. Plombon

IPC分类号： H01L29/775 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

CPC分类号： H01L29/775 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66969

摘要： A transistor device may include a first perovskite gate material, a first perovskite ferroelectric material on the first gate material, a first perovskite semiconductor material on the first ferroelectric material, a second perovskite ferroelectric material on the first semiconductor material, a second perovskite gate material on the second ferroelectric material, a third perovskite ferroelectric material on the second gate material, a second perovskite semiconductor material on the third ferroelectric material, a fourth perovskite ferroelectric material on the second semiconductor material, a third perovskite gate material on the fourth ferroelectric material, a first source/drain metal adjacent a first side of each of the first semiconductor material and the second semiconductor material, a second source/drain metal adjacent a second side opposite the first side of each of the first semiconductor material and the second semiconductor material, and dielectric materials between the source/drain metals and the gate materials.

公开(公告)号：US20240222126A1

公开(公告)日：2024-07-04

申请号：US18147644

申请日：2022-12-28

申请人： Intel Corporation

发明人： Mahmut Sami Kavrik ,  Uygar Avci ,  Brandon Holybee ,  Jennifer Lux ,  Kevin O'Brien ,  Shida Tan

IPC分类号： H01L21/266 ,  H01L21/265

CPC分类号： H01L21/266 ,  H01L21/26506

摘要： This disclosure describes systems, apparatus, methods, and devices related to fabrication using ion beams. The device may apply an ion beam targeted to at least one of one or more regions of a top layer, a metal layer placed on top of the top layer, or one or more ion stoppers placed on top of the top layer, wherein the ion beam is tuned using a predetermined energy range or a dosing level of ions to modify the material characteristics of the 2D material at the one or more regions of the top layer. The device may create a bond between the one or more 2D and metal layers to the one or more regions of the top layer where the material characteristics of the 2D material have been modified due to the impinging ion beam.

公开(公告)号：US20240222073A1

公开(公告)日：2024-07-04

申请号：US18147636

申请日：2022-12-28

申请人： Intel Corporation

发明人： Shida Tan ,  Uygar Avci ,  Brandon Holybee ,  Kirby Maxey ,  Kevin O'Brien ,  Mahmut Sami Kavrik

IPC分类号： H01J37/317 ,  H01L21/027 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213

CPC分类号： H01J37/3174 ,  H01L21/0279 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32135 ,  H01L21/32139 ,  H01J2237/3174 ,  H01J2237/31755

摘要： This disclosure describes systems, apparatus, methods, and devices related to ion beams fabrication. A device may overlay a wafer assembly of one or more layers with a top layer comprised of a material having 2D material characteristics. The device may be fabricated by applying an ion beam targeted to at least one of one or more regions of the top layer or a resist layer placed on top of the top layer, wherein the ion beam is tuned using a predetermined energy range or a dosing level of ions to modify material characteristics of the resist layer or to perform milling of the top layer or other layers of the one or more layers of the wafer assembly.

公开(公告)号：US20240120415A1

公开(公告)日：2024-04-11

申请号：US17958362

申请日：2022-10-01

申请人： Intel Corporation

发明人： Scott B. Clendenning ,  Sudarat Lee ,  Kevin P. O'Brien ,  Rachel A. Steinhardt ,  John J. Plombon ,  Arnab Sen Gupta ,  Charles C. Mokhtarzadeh ,  Gauri Auluck ,  Tristan A. Tronic ,  Brandon Holybee ,  Matthew V. Metz ,  Dmitri Evgenievich Nikonov ,  Ian Alexander Young

IPC分类号： H01L29/778 ,  H01L21/02 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/778 ,  H01L21/02197 ,  H01L29/0665 ,  H01L29/66795 ,  H01L29/78391

摘要： Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a perovskite stack is grown on a buffer layer as part of manufacturing a transistor. The perovskite stack includes one or more doped semiconductor layers alternating with other lattice-matched layers. Growing the doped semiconductor layers on lattice-matched layers can improve the quality of the doped semiconductor layers. The lattice-matched layers can be etched away, leaving the doped semiconductor layers as fins for a ribbon FET. A ferroelectric layer can be conformally grown on the fins, creating a high-quality ferroelectric layer above and below the fins. A gate can then be grown on the ferroelectric layer.

公开(公告)号：US20240113220A1

公开(公告)日：2024-04-04

申请号：US17958094

申请日：2022-09-30

申请人： Intel Corporation

发明人： Arnab Sen Gupta ,  Ian Alexander Young ,  Dmitri Evgenievich Nikonov ,  Marko Radosavljevic ,  Matthew V. Metz ,  John J. Plombon ,  Raseong Kim ,  Uygar E. Avci ,  Kevin P. O'Brien ,  Scott B. Clendenning ,  Jason C. Retasket ,  Shriram Shivaraman ,  Dominique A. Adams ,  Carly Rogan ,  Punyashloka Debashis ,  Brandon Holybee ,  Rachel A. Steinhardt ,  Sudarat Lee

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L29/20 ,  H01L29/24 ,  H01L29/51 ,  H01L29/66 ,  H01L29/76

CPC分类号： H01L29/78391 ,  H01L21/0254 ,  H01L21/02568 ,  H01L21/0262 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/516 ,  H01L29/66522 ,  H01L29/6684 ,  H01L29/66969 ,  H01L29/7606

摘要： Technologies for a transistor with a thin-film ferroelectric gate dielectric are disclosed. In the illustrative embodiment, a transistor has a thin layer of scandium aluminum nitride (ScxAl1-xN) ferroelectric gate dielectric. The channel of the transistor may be, e.g., gallium nitride or molybdenum disulfide. In one embodiment, the ferroelectric polarization changes when voltage is applied and removed from a gate electrode, facilitating switching of the transistor at a lower applied voltage. In another embodiment, the ferroelectric polarization of a gate dielectric of a transistor changes when the voltage is past a positive threshold value or a negative threshold value. Such a transistor can be used as a one-transistor memory cell.

公开(公告)号：US20240113212A1

公开(公告)日：2024-04-04

申请号：US17956296

申请日：2022-09-29

申请人： Intel Corporation

发明人： Ian Alexander Young ,  Dmitri Evgenievich Nikonov ,  Marko Radosavljevic ,  Matthew V. Metz ,  John J. Plombon ,  Raseong Kim ,  Kevin P. O'Brien ,  Scott B. Clendenning ,  Tristan A. Tronic ,  Dominique A. Adams ,  Carly Rogan ,  Hai Li ,  Arnab Sen Gupta ,  Gauri Auluck ,  I-Cheng Tung ,  Brandon Holybee ,  Rachel A. Steinhardt ,  Punyashloka Debashis

IPC分类号： H01L29/775 ,  H01L21/02 ,  H01L21/465 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

CPC分类号： H01L29/775 ,  H01L21/02565 ,  H01L21/02603 ,  H01L21/465 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66969

摘要： Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a perovskite stack is grown on a buffer layer as part of manufacturing a transistor. The perovskite stack includes one or more doped semiconductor layers alternating with other lattice-matched layers, such as undoped semiconductor layers. Growing the doped semiconductor layers on lattice-matched layers can improve the quality of the doped semiconductor layers. The lattice-matched layers can be preferentially etched away, leaving the doped semiconductor layers as fins for a ribbon FET. In another embodiment, an interlayer can be deposited on top of a semiconductor layer, and a ferroelectric layer can be deposited on the interlayer. The interlayer can bridge a gap in lattice parameters between the semiconductor layer and the ferroelectric layer.

公开(公告)号：US20240097031A1

公开(公告)日：2024-03-21

申请号：US17947071

申请日：2022-09-16

申请人： Intel Corporation

发明人： Punyashloka Debashis ,  Rachel A. Steinhardt ,  Brandon Holybee ,  Kevin P. O'Brien ,  Dmitri Evgenievich Nikonov ,  John J. Plombon ,  Ian Alexander Young ,  Raseong Kim ,  Carly Rogan ,  Dominique A. Adams ,  Arnab Sen Gupta ,  Marko Radosavljevic ,  Scott B. Clendenning ,  Gauri Auluck ,  Hai Li ,  Matthew V. Metz ,  Tristan A. Tronic ,  I-Cheng Tung

IPC分类号： H01L29/78 ,  H01L29/51

CPC分类号： H01L29/78391 ,  H01L29/516

摘要： In one embodiment, a transistor device includes a gate material layer on a substrate, a ferroelectric (FE) material layer on the gate material, a semiconductor channel material layer on the FE material layer, a first source/drain material on the FE material layer and adjacent the semiconductor channel material layer, and a second source/drain material on the FE material layer and adjacent the semiconductor channel material layer and on an opposite side of the semiconductor channel material layer from the first source/drain material. A first portion of the FE material layer is directly between the gate material and the first source/drain material, and a second portion of the FE material layer is directly between the gate material and the second source/drain material.