Invention Publication
- Patent Title: VICTIM CACHE THAT SUPPORTS DRAINING WRITE-MISS ENTRIES
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Application No.: US18639013Application Date: 2024-04-18
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Publication No.: US20240264952A1Publication Date: 2024-08-08
- Inventor: Naveen BHORIA , Timothy David ANDERSON , Pete HIPPLEHEUSER
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Main IPC: G06F12/128
- IPC: G06F12/128 ; G06F9/30 ; G06F9/54 ; G06F11/10 ; G06F12/02 ; G06F12/0802 ; G06F12/0804 ; G06F12/0806 ; G06F12/0811 ; G06F12/0815 ; G06F12/0817 ; G06F12/0853 ; G06F12/0855 ; G06F12/0864 ; G06F12/0884 ; G06F12/0888 ; G06F12/0891 ; G06F12/0895 ; G06F12/0897 ; G06F12/12 ; G06F12/121 ; G06F12/126 ; G06F12/127 ; G06F13/16 ; G06F15/80 ; G11C5/06 ; G11C7/10 ; G11C7/22 ; G11C29/42 ; G11C29/44
Abstract:
A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes a set of cache lines, line type bits configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data, and an eviction controller configured to flush stored write-miss data based on the line type bits.
Information query
IPC分类:
