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发明授权
US6064244A Phase-locked loop circuit permitting reduction of circuit size 失效
锁相环电路允许减小电路尺寸

Phase-locked loop circuit permitting reduction of circuit size
摘要：
A phase-locked loop circuit is constituted in such a manner that a delayed signal created by causing an input signal to loop through a delay stage a plurality of times is compared in terms of phase with the input signal, and an amount of delay in the delay stage is controlled in accordance with the comparison result of the delayed signal and the input signal. Therefore, the circuit size can be reduced with a reduced number of delay units constituting the delay stage.
摘要（中）：

锁相环电路以这样的方式构成，使得通过使输入信号多次循环延迟级而产生的延迟信号在与输入信号的相位方面进行比较，并且在 根据延迟信号和输入信号的比较结果控制延迟级。 因此，可以减少构成延迟级的延迟单元的数量来减小电路尺寸。

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