发明授权
- 专利标题: Semiconductor integrated circuit device
- 专利标题(中): 半导体集成电路器件
-
申请号: US376468申请日: 1999-08-18
-
公开(公告)号: US6091660A公开(公告)日: 2000-07-18
- 发明人: Toshio Sasaki , Yuji Tanaka , Kazumasa Yanagisawa , Hitoshi Tanaka , Jun Sato , Takashi Miyamoto , Mariko Ohtsuka , Satoru Nakanishi , Kazushige Ayukawa , Takao Watanabe
- 申请人: Toshio Sasaki , Yuji Tanaka , Kazumasa Yanagisawa , Hitoshi Tanaka , Jun Sato , Takashi Miyamoto , Mariko Ohtsuka , Satoru Nakanishi , Kazushige Ayukawa , Takao Watanabe
- 申请人地址: JPX Tokyo JPX Tokyo
- 专利权人: Hitachi, Ltd.,Hitachi USLI Systems Co., Ltd.
- 当前专利权人: Hitachi, Ltd.,Hitachi USLI Systems Co., Ltd.
- 当前专利权人地址: JPX Tokyo JPX Tokyo
- 优先权: JPX9-286118 19971002
- 主分类号: G11C11/401
- IPC分类号: G11C11/401 ; G11C8/00 ; G11C8/12 ; G11C11/407
摘要:
A RAM mounted so as to mix with logic circuits has a plurality of memory mats and one control circuit provided for the plurality of memory mats. Arithmetic circuits for respectively performing +1 or -1 arithmetic operations are respectively provided so as to correspond to the respective memory mats and are electrically connected in cascade form. An input terminal of the initial-stage arithmetic circuit is supplied with address-setting fixed address signals. Input signals supplied to the next and subsequent arithmetic circuits or signals outputted therefrom are defined as own-assigned address signals (those assigned to the corresponding memory mats). A comparator provided in association with each arithmetic circuit referred to above makes comparisons for coincidence between the address signals and address signals input upon memory access. The corresponding memory mat is selected based on the resultant coincidence signal.
公开/授权文献
信息查询