利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

215 条记录 (耗时 0.047 秒)

    Semiconductor integrated circuit device
    1.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US6091660A

    公开(公告)日：2000-07-18

    申请号：US376468

    申请日：1999-08-18

    申请人： Toshio Sasaki ,  Yuji Tanaka ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka ,  Jun Sato ,  Takashi Miyamoto ,  Mariko Ohtsuka ,  Satoru Nakanishi ,  Kazushige Ayukawa ,  Takao Watanabe

    发明人： Toshio Sasaki ,  Yuji Tanaka ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka ,  Jun Sato ,  Takashi Miyamoto ,  Mariko Ohtsuka ,  Satoru Nakanishi ,  Kazushige Ayukawa ,  Takao Watanabe

    IPC分类号： G11C11/401 ,  G11C8/00 ,  G11C8/12 ,  G11C11/407

    CPC分类号： G11C8/12

    摘要： A RAM mounted so as to mix with logic circuits has a plurality of memory mats and one control circuit provided for the plurality of memory mats. Arithmetic circuits for respectively performing +1 or -1 arithmetic operations are respectively provided so as to correspond to the respective memory mats and are electrically connected in cascade form. An input terminal of the initial-stage arithmetic circuit is supplied with address-setting fixed address signals. Input signals supplied to the next and subsequent arithmetic circuits or signals outputted therefrom are defined as own-assigned address signals (those assigned to the corresponding memory mats). A comparator provided in association with each arithmetic circuit referred to above makes comparisons for coincidence between the address signals and address signals input upon memory access. The corresponding memory mat is selected based on the resultant coincidence signal.

    摘要翻译： 安装成与逻辑电路混合的RAM具有多个存储器垫和为多个存储器垫提供的一个控制电路。 分别提供用于分别执行+1或-1算术运算的算术电路，以便对应于相应的存储器垫并且以级联形式电连接。 初始级算术电路的输入端被提供地址设定固定地址信号。 提供给下一个和后续运算电路的输入信号或从其输出的信号被定义为自己分配的地址信号（分配给相应的存储器垫的那些）。 与上述每个运算电路相关联地提供的比较器比较了存储器访问时输入的地址信号和地址信号之间的一致性。 基于所得到的一致信号来选择相应的存储器垫。

    Semiconductor integrated circuit device
    2.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US06314044B1

    公开(公告)日：2001-11-06

    申请号：US09594840

    申请日：2000-06-15

    申请人： Toshio Sasaki ,  Yuji Tanaka ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka ,  Jun Sato ,  Takashi Miyamoto ,  Mariko Ohtsuka ,  Satoru Nakanishi ,  Kazushige Ayukawa ,  Takao Watanabe

    发明人： Toshio Sasaki ,  Yuji Tanaka ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka ,  Jun Sato ,  Takashi Miyamoto ,  Mariko Ohtsuka ,  Satoru Nakanishi ,  Kazushige Ayukawa ,  Takao Watanabe

    IPC分类号： G11C800

    CPC分类号： G11C8/12

    摘要： A RAM mounted so as to mix with logic circuits has a plurality of memory mats and one control circuit provided for the plurality of memory mats. Arithmetic circuits for respectively performing +1 or −1 arithmetic operation are respectively provided so as to correspond to the respective memory mats and are electrically connected in cascade form. An input terminal of the initial-stage arithmetic circuit is supplied with address-setting fixed address signals. Input signals supplied to the next and subsequent arithmetic circuits or signals outputted therefrom are defined as own-assigned address signals (those assigned to the corresponding memory mats). A comparator provided in association with each arithmetic circuit referred to above makes comparisons for coincidence between the address signals and address signals input upon memory access. The corresponding memory mat is selected based on the resultant coincidence signal.

    摘要翻译： 安装成与逻辑电路混合的RAM具有多个存储器垫和为多个存储器垫提供的一个控制电路。 分别提供用于分别执行+1或-1运算的算术电路，以对应于相应的存储器垫并且以级联形式电连接。 初始级算术电路的输入端被提供地址设定固定地址信号。 提供给下一个和后续运算电路的输入信号或从其输出的信号被定义为自己分配的地址信号（分配给相应的存储器垫的那些）。 与上述每个运算电路相关联地提供的比较器比较了存储器访问时输入的地址信号和地址信号之间的一致性。 基于所得到的一致信号来选择相应的存储器垫。

    Manually-operated loading and ejecting mechanism for a magnetic tape cassette apparatus
    6.
    发明授权
    Manually-operated loading and ejecting mechanism for a magnetic tape cassette apparatus 失效
    用于磁带盒装置的手动装载和排出机构

    公开(公告)号：US5032940A

    公开(公告)日：1991-07-16

    申请号：US340225

    申请日：1989-04-19

    申请人： Takao Watanabe ,  Takashi Miyamoto

    发明人： Takao Watanabe ,  Takashi Miyamoto

    IPC分类号： G11B15/675

    CPC分类号： G11B15/67513

    摘要： A data transfer apparatus has a casing with an entrance slot in which a magnetic tape cassette is to be inserted. Upon full insertion of the cassette to a preassigned standby position, a cassette shift mechanism is activated to transport the cassette from the standby position to a data transfer position opposite a substantially fixed magnetic head. A load/eject lever on the front panel of the casing is to be manually turned following the shifting of the cassette to the data transfer position, in order to cause a pair of drive spindles to move into driving engagement with the hubs of the cassette. Since the drive spindles remain retracted, instead of being automatically sprung into driving engagement with the cassette hubs, unless the load/eject lever is manipulated following the shifting of the cassette to the data transfer position, a cleaning cassette can be used with the apparatus for cleaning the magnetic head without the danger of ruining the drive spindles as a result of forced contact with the cleaning cassette.

    摘要翻译： 数据传送装置具有壳体，其具有插入磁带盒的入口槽。 当磁带盒完全插入预先分配的待机位置时，磁带盒移动机构被启动，以将磁带从待机位置传送到数据传送位置，与数字传输位置相对的是基本固定的磁头。 在盒子移动到数据传送位置之后，手动前进面板上的装载/弹出杆将被手动转动，以便使一对驱动主轴移动成与盒的毂相配合。 由于驱动器主轴保持缩回，而不是自动地弹出与盒毂的驱动接合，除非在将盒移动到数据传送位置之后操纵装载/弹出杆，否则可以使用清洁盒与装置 清洁磁头，不会因为与清洁带强行接触而导致驱动主轴损坏。

    Data processing apparatus having DRAM incorporated therein
    7.
    发明授权
    Data processing apparatus having DRAM incorporated therein 有权
    具有并入其中的DRAM的数据处理装置

    公开(公告)号：US06295074B1

    公开(公告)日：2001-09-25

    申请号：US09142923

    申请日：1998-09-18

    申请人： Kazushige Yamagishi ,  Jun Sato ,  Takashi Miyamoto

    发明人： Kazushige Yamagishi ,  Jun Sato ,  Takashi Miyamoto

    IPC分类号： G06F1576

    CPC分类号： G06T1/20 ,  G09G5/363

    摘要： The present invention can be introduced to an architecture such as a personal computer or an amusement equipment for realizing a high-speed graphic processing. In the case where a frame buffer, a command memory and an image processor are integrated in one chip in order to improve the drawing performance of an image processing device, each of the frame buffer and the command memory is constructed by a plurality of identical memory modules and the same row address is allotted to each memory module, thereby increasing the memory address depth. Thereby, it is possible to realize an incorporated frame buffer and an incorporated command memory each of which has a large capacity when seen from the image processor.

    摘要翻译： 本发明可以被引入到用于实现高速图形处理的诸如个人计算机或娱乐设备的体系结构中。 在为了提高图像处理装置的绘图性能而将帧缓冲器，命令存储器和图像处理器集成在一个芯片中的情况下，帧缓冲器和命令存储器中的每一个由多个相同的存储器 模块和相同的行地址被分配给每个存储器模块，从而增加存储器地址深度。 由此，可以实现从图像处理器看时具有大容量的并入帧缓冲器和内置指令存储器。

    Data processing apparatus having DRAM incorporated therein
    8.
    发明授权
    Data processing apparatus having DRAM incorporated therein 失效
    具有并入其中的DRAM的数据处理装置

    公开(公告)号：US06744437B2

    公开(公告)日：2004-06-01

    申请号：US10284153

    申请日：2002-10-31

    申请人： Kazushige Yamagishi ,  Jun Sato ,  Takashi Miyamoto

    发明人： Kazushige Yamagishi ,  Jun Sato ,  Takashi Miyamoto

    IPC分类号： G06F1576

    CPC分类号： G11C7/1006 ,  G09G5/39 ,  G09G5/393 ,  G09G5/399 ,  G09G2360/127 ,  G09G2360/128

    摘要： The present invention can be introduced to an architecture such as a personal computer or an amusement equipment for realizing a high-speed graphic processing. In the case where a frame buffer, a command memory and an image processor are integrated in one chip in order to improve the drawing performance of an image processing device, each of the frame buffer and the command memory is constructed by a plurality of identical memory modules and the same row address is allotted to each memory module, thereby increasing the memory address depth. Thereby, it is possible to realize an incorporated frame buffer and an incorporated command memory each of which has a large capacity when seen from the image processor.

    摘要翻译： 本发明可以被引入到用于实现高速图形处理的诸如个人计算机或娱乐设备的体系结构中。 在为了提高图像处理装置的绘图性能而将帧缓冲器，命令存储器和图像处理器集成在一个芯片中的情况下，帧缓冲器和命令存储器中的每一个由多个相同的存储器 模块和相同的行地址被分配给每个存储器模块，从而增加存储器地址深度。 由此，可以实现从图像处理器看时具有大容量的并入帧缓冲器和内置指令存储器。

    Data processing apparatus having DRAM incorporated therein
    10.
    发明授权
    Data processing apparatus having DRAM incorporated therein 失效
    其中并入有DRAM的数据处理装置

    公开(公告)号：US06496610B2

    公开(公告)日：2002-12-17

    申请号：US09142905

    申请日：1998-09-18

    申请人： Kazushige Yamagishi ,  Jun Sato ,  Takashi Miyamoto

    发明人： Kazushige Yamagishi ,  Jun Sato ,  Takashi Miyamoto

    IPC分类号： G06K954

    CPC分类号： G11C5/025 ,  G06F15/7842 ,  G06F15/7857 ,  G11C7/1072

    摘要： The present invention may be introduced to an architecture such as a personal computer or an amusement equipment for realizing a high-speed graphic processing and provides an optimum arrangement along the flow of information in the case where a frame buffer, a command memory and an image processor are incorporated in one chip in order to improve the drawing performance of an image processing device. Thereby, unnecessary drawing-around of wiring is eliminated and it is possible to reduce the chip area. Further, since the wiring length is shortened, signal delay becomes small, thereby enabling a high-speed operation.

    摘要翻译： 本发明可以被引入诸如个人计算机或用于实现高速图形处理的娱乐设备的架构，并且在帧缓冲器，命令存储器和图像的情况下沿着信息流提供最佳布置 处理器被并入一个芯片中，以便提高图像处理装置的绘制性能。 由此，消除了布线的不必要的卷绕，并且可以减小芯片面积。 此外，由于布线长度缩短，信号延迟变小，能够实现高速运转。