公开(公告)号：US06314044B1

公开(公告)日：2001-11-06

申请号：US09594840

申请日：2000-06-15

申请人： Toshio Sasaki ,  Yuji Tanaka ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka ,  Jun Sato ,  Takashi Miyamoto ,  Mariko Ohtsuka ,  Satoru Nakanishi ,  Kazushige Ayukawa ,  Takao Watanabe

发明人： Toshio Sasaki ,  Yuji Tanaka ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka ,  Jun Sato ,  Takashi Miyamoto ,  Mariko Ohtsuka ,  Satoru Nakanishi ,  Kazushige Ayukawa ,  Takao Watanabe

IPC分类号： G11C800

CPC分类号： G11C8/12

摘要： A RAM mounted so as to mix with logic circuits has a plurality of memory mats and one control circuit provided for the plurality of memory mats. Arithmetic circuits for respectively performing +1 or −1 arithmetic operation are respectively provided so as to correspond to the respective memory mats and are electrically connected in cascade form. An input terminal of the initial-stage arithmetic circuit is supplied with address-setting fixed address signals. Input signals supplied to the next and subsequent arithmetic circuits or signals outputted therefrom are defined as own-assigned address signals (those assigned to the corresponding memory mats). A comparator provided in association with each arithmetic circuit referred to above makes comparisons for coincidence between the address signals and address signals input upon memory access. The corresponding memory mat is selected based on the resultant coincidence signal.

摘要翻译： 安装成与逻辑电路混合的RAM具有多个存储器垫和为多个存储器垫提供的一个控制电路。 分别提供用于分别执行+1或-1运算的算术电路，以对应于相应的存储器垫并且以级联形式电连接。 初始级算术电路的输入端被提供地址设定固定地址信号。 提供给下一个和后续运算电路的输入信号或从其输出的信号被定义为自己分配的地址信号（分配给相应的存储器垫的那些）。 与上述每个运算电路相关联地提供的比较器比较了存储器访问时输入的地址信号和地址信号之间的一致性。 基于所得到的一致信号来选择相应的存储器垫。

公开(公告)号：US6091660A

公开(公告)日：2000-07-18

申请号：US376468

申请日：1999-08-18

申请人： Toshio Sasaki ,  Yuji Tanaka ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka ,  Jun Sato ,  Takashi Miyamoto ,  Mariko Ohtsuka ,  Satoru Nakanishi ,  Kazushige Ayukawa ,  Takao Watanabe

发明人： Toshio Sasaki ,  Yuji Tanaka ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka ,  Jun Sato ,  Takashi Miyamoto ,  Mariko Ohtsuka ,  Satoru Nakanishi ,  Kazushige Ayukawa ,  Takao Watanabe

IPC分类号： G11C11/401 ,  G11C8/00 ,  G11C8/12 ,  G11C11/407

CPC分类号： G11C8/12

摘要： A RAM mounted so as to mix with logic circuits has a plurality of memory mats and one control circuit provided for the plurality of memory mats. Arithmetic circuits for respectively performing +1 or -1 arithmetic operations are respectively provided so as to correspond to the respective memory mats and are electrically connected in cascade form. An input terminal of the initial-stage arithmetic circuit is supplied with address-setting fixed address signals. Input signals supplied to the next and subsequent arithmetic circuits or signals outputted therefrom are defined as own-assigned address signals (those assigned to the corresponding memory mats). A comparator provided in association with each arithmetic circuit referred to above makes comparisons for coincidence between the address signals and address signals input upon memory access. The corresponding memory mat is selected based on the resultant coincidence signal.

摘要翻译： 安装成与逻辑电路混合的RAM具有多个存储器垫和为多个存储器垫提供的一个控制电路。 分别提供用于分别执行+1或-1算术运算的算术电路，以便对应于相应的存储器垫并且以级联形式电连接。 初始级算术电路的输入端被提供地址设定固定地址信号。 提供给下一个和后续运算电路的输入信号或从其输出的信号被定义为自己分配的地址信号（分配给相应的存储器垫的那些）。 与上述每个运算电路相关联地提供的比较器比较了存储器访问时输入的地址信号和地址信号之间的一致性。 基于所得到的一致信号来选择相应的存储器垫。

公开(公告)号：US5978305A

公开(公告)日：1999-11-02

申请号：US165194

申请日：1998-10-02

申请人： Toshio Sasaki ,  Yuji Tanaka ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka ,  Jun Sato ,  Takashi Miyamoto ,  Mariko Ohtsuka ,  Satoru Nakanishi ,  Kazushige Ayukawa ,  Takao Watanabe

发明人： Toshio Sasaki ,  Yuji Tanaka ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka ,  Jun Sato ,  Takashi Miyamoto ,  Mariko Ohtsuka ,  Satoru Nakanishi ,  Kazushige Ayukawa ,  Takao Watanabe

IPC分类号： G11C11/401 ,  G11C8/00 ,  G11C8/12 ,  G11C11/407 ,  G11C7/00

CPC分类号： G11C8/12

摘要： A RAM mounted so as to mix with logic circuits has a plurality of memory mats and one control circuit provided for the plurality of memory mats. Arithmetic circuits for respectively performing +1 or -1 arithmetic operations are respectively provided so as to correspond to the respective memory mats and are electrically connected in cascade form. An input terminal of the initial-stage arithmetic circuit is supplied with address-setting fixed address signals. Input signals supplied to the next and subsequent arithmetic circuits or signals outputted therefrom are defined as own-assigned address signals (those assigned to the corresponding memory mats). A comparator provided in association with each arithmetic circuit referred to above makes comparisons for coincidence between the address signals and address signals input upon memory access. The corresponding memory mat is selected based on the resultant coincidence signal.

公开(公告)号：US06301184B1

公开(公告)日：2001-10-09

申请号：US09480695

申请日：2000-01-11

申请人： Toshio Sasaki ,  Yoshihiko Yasu ,  Kazumasa Yanagisawa ,  Yuji Tanaka ,  Toshiaki Takahira ,  Yasuto Igarashi ,  Mariko Ohtsuka ,  Yasunobu Aoki

发明人： Toshio Sasaki ,  Yoshihiko Yasu ,  Kazumasa Yanagisawa ,  Yuji Tanaka ,  Toshiaki Takahira ,  Yasuto Igarashi ,  Mariko Ohtsuka ,  Yasunobu Aoki

IPC分类号： G11C800

CPC分类号： G11C11/4074 ,  G11C7/1045

摘要： A DRAM module is applied to the system LSI which is provided with a standby mode for suppressing the whole operation thereof and an operation standby mode which permits at least the DRAM module to operate but suppresses the operation of other circuits. The above-mentioned modes as well as a substrate bias control technology are applied to the CMOS system LSI that operates on a low voltage. The system LSI is controlled to hold or not to hold data, enabling a memory of a large capacity to be mounted and consuming a sufficiently decreased amount of electric power.

摘要翻译： 将DRAM模块应用于具有用于抑制其整体操作的待机模式的系统LSI和至少允许DRAM模块操作但抑制其它电路的操作的操作待机模式。 将上述模式以及衬底偏置控制技术应用于在低电压下工作的CMOS系统LSI。 控制系统LSI以保持或不保存数据，使得能够安装大容量的存储器并消耗足够的电力量。

公开(公告)号：US09126853B2

公开(公告)日：2015-09-08

申请号：US13391354

申请日：2010-05-25

申请人： Hironobu Suzuki ,  Yuji Tanaka ,  Hiroo Takabatake ,  Yoshisuke Nakamura

发明人： Hironobu Suzuki ,  Yuji Tanaka ,  Hiroo Takabatake ,  Yoshisuke Nakamura

IPC分类号： B01D61/12 ,  B01D61/20 ,  B01D61/22 ,  C02F1/44 ,  G05D11/03 ,  B01F3/08 ,  B01D61/02 ,  C02F103/02 ,  C02F103/04

CPC分类号： C02F1/44 ,  B01D61/02 ,  B01D61/12 ,  B01D61/20 ,  B01D61/22 ,  B01D2317/022 ,  B01D2317/04 ,  B01F3/0865 ,  B01F3/088 ,  C02F1/441 ,  C02F1/442 ,  C02F2103/02 ,  C02F2103/04 ,  C02F2301/08 ,  G05D11/03

摘要： Disclosed is a fresh water generator for fresh water production, which is effective to prevent a membrane life from becoming worse by suppressing the load on the membrane of a second semi-permeable membrane treatment facility when the concentrated water produced by the treatment of a first semi-permeable membrane treatment facility, and water to be treated with different osmotic pressure there from are mixed and treated with the second semi-permeable membrane treatment facility by the fresh water generator which comprises a means for storing the concentrated water produced from the first semi-permeable membrane treatment facility and water (B) to be treated, which is separately supplied in a storage tank A and a storage tank B in such a manner that the flow rate (mixture ratio) of the concentrated water to the water (B) to be treated is maintained constant, and supplying the concentrated water and the water (B) to be treated from each of the storage tanks to the second semi-permeable membrane treatment facility at a predetermined flow rate in at least a treatment process for treating water (A) to be treated with the first semi-permeable membrane treatment facility so as to obtain fresh water.

摘要翻译： 公开了一种用于淡水生产的淡水发生器，当通过处理第一半透明膜处理设备产生的浓缩水时，通过抑制第二半透膜处理设备的膜上的负荷来有效地防止膜寿命变差 渗透膜处理设备，以及其中渗透压不同的待处理水将由所述第二半渗透膜处理设备进行混合处理，所述净水器包括用于储存由所述第一半透膜处理设备产生的浓缩水的装置， 渗透膜处理装置和待处理的水（B），其分别供给到储罐A和储罐B中，使得浓缩水与水（B）的流量（混合比）（B）相对于 被处理保持恒定，并将待处理的浓缩水和水（B）从每个储存罐供应到第二半渗透性m 至少在处理用第一半透膜处理设备处理的水（A）的处理过程中以预定的流量进行污水处理设备以获得淡水。

公开(公告)号：US20140055964A1

公开(公告)日：2014-02-27

申请号：US13983169

申请日：2012-12-14

申请人： Takashi Osako ,  Yuji Tanaka

发明人： Takashi Osako ,  Yuji Tanaka

IPC分类号： H05K1/11

CPC分类号： H05K1/118 ,  H01B1/22 ,  H01L27/3276 ,  H01L2251/5338 ,  H05B33/22 ,  H05K3/323 ,  H05K3/361 ,  H05K2201/0221

摘要： A flexible display device comprises a device substrate and a flexible circuit substrate, and achieves high reliability of electrical connection. The device substrate includes a flexible substrate, a display unit and a first terminal part. The flexible circuit substrate includes a second terminal part. An ACF including conductive particles connects the first and second terminal parts. Each conductive particle consists of a core part covered by a metal layer. An electrode layer and a cushioning layer are provided between the flexible substrate and the first terminal part. A quotient of a sum of a product of average particle diameter and elastic modulus for the core part, and a product of double average thickness and elastic modulus for the metal layer, divided by a sum of products of average thickness and elastic modulus for the first terminal part, the cushioning layer and the electrode layer, is no greater than 1.5.

摘要翻译： 柔性显示装置包括器件基板和柔性电路基板，并实现电连接的高可靠性。 器件基板包括柔性基板，显示单元和第一端子部件。 柔性电路基板包括第二端子部。 包括导电颗粒的ACF连接第一和第二端子部分。 每个导电颗粒由覆盖有金属层的核心部分组成。 在柔性基板和第一端子部之间设置电极层和缓冲层。 核心部分的平均粒径和弹性模量的乘积之和以及金属层的双重平均厚度和弹性模量的乘积除以第一次的平均厚度和弹性模量的乘积之和 端子部分，缓冲层和电极层，不大于1.5。

公开(公告)号：US20130330787A1

公开(公告)日：2013-12-12

申请号：US13992443

申请日：2011-12-08

申请人： Satoko Kanamori ,  Jihoon Cheon ,  Takashi Mimitsuka ,  Norihiro Takeuchi ,  Makoto Nishida ,  Yuji Tanaka

发明人： Satoko Kanamori ,  Jihoon Cheon ,  Takashi Mimitsuka ,  Norihiro Takeuchi ,  Makoto Nishida ,  Yuji Tanaka

IPC分类号： C12P13/08 ,  C12P7/56

CPC分类号： C12P13/08 ,  C12M29/02 ,  C12M29/18 ,  C12M33/14 ,  C12M41/40 ,  C12M47/10 ,  C12P7/40 ,  C12P7/56 ,  C12P13/001 ,  C12P13/04

摘要： A method produces a chemical through continuous fermentation including: (a) culturing a cell in a culture medium in a fermentor to ferment a feedstock to produce a chemical; (b) conducting filtration of the culture medium with a separation membrane module; (c) separating a permeate containing the chemical from the culture medium while retaining a non-permeated liquid in the fermentor, and (d) supplying a gas from at least one of a lower portion of the separation membrane module and a pipe communicating between the fermentor and the separation membrane module to adjust a gas linear velocity in the separation membrane module to 0.15 cm/s to 70 cm/s while supplying the separation membrane module with a liquid.

摘要翻译： 方法通过连续发酵生产化学品，包括：（a）在发酵罐中培养培养基中的细胞以发酵原料以生产化学品; （b）用分离膜组件对培养基进行过滤; （c）将含有化学物质的渗透物从培养基中分离，同时将不渗透的液体保持在发酵罐中，和（d）从分离膜组件的下部中的至少一个供给气体， 发酵罐和分离膜组件，将分离膜组件中的气体线速度调节至0.15厘米/秒至70厘米/秒，同时向分离膜组件供应液体。

公开(公告)号：US20130280767A1

公开(公告)日：2013-10-24

申请号：US13976642

申请日：2011-12-22

申请人： Atsushi Kobayashi ,  Jihoon Cheon ,  Norihiro Takeuchi ,  Makoto Nishida ,  Yuji Tanaka

发明人： Atsushi Kobayashi ,  Jihoon Cheon ,  Norihiro Takeuchi ,  Makoto Nishida ,  Yuji Tanaka

IPC分类号： C12M1/00

CPC分类号： C12M47/10 ,  B01D63/02 ,  B01D69/02 ,  B01D69/08 ,  B01D71/68 ,  B01D2313/04

摘要： A hollow fiber membrane module includes a housing, a hollow fiber membrane sealed in the housing and a sealing agent in a space between the hollow fiber membrane and the housing, wherein 1) the hollow fiber membrane is made of a polysulfone based resin; 2) a membrane surface average pore diameter is 5 nm or more and 500 nm or less; 3) a pure water permeability coefficient under 50 kPa at 25° C. is 0.05 m3/m2/hour or more and 5 m3/m2/hour or less; 4) the sealing agent is at least one selected from the group consisting of a polyurethane resin and an epoxy resin; and 5) a decrease in tensile strength after bringing the sealing agent into contact with saturated steam at 121° C. for 24 hours is 25% or less.

摘要翻译： 中空纤维膜组件包括壳体，密封在壳体中的中空纤维膜和在中空纤维膜和壳体之间的空间中的密封剂，其中1）中空纤维膜由聚砜基树脂制成; 2）膜表面平均孔径为5nm以上且500nm以下; 3）在25℃下50kPa下的纯水渗透系数为0.05m 3 / m 2 /小时以上，5m 3 / m 2 /小时以下; 4）密封剂是选自聚氨酯树脂和环氧树脂中的至少一种; 和5）使密封剂在121℃与饱和蒸汽接触24小时后的拉伸强度降低为25％以下。

公开(公告)号：US08478395B2

公开(公告)日：2013-07-02

申请号：US12921069

申请日：2009-03-03

申请人： Masafumi Uematsu ,  Takashi Kitaoka ,  Koji Nishida ,  Yuji Tanaka ,  Matsuhiko Nishizawa ,  Hirokazu Kaji ,  Soichiro Sekine

发明人： Masafumi Uematsu ,  Takashi Kitaoka ,  Koji Nishida ,  Yuji Tanaka ,  Matsuhiko Nishizawa ,  Hirokazu Kaji ,  Soichiro Sekine

IPC分类号： A61B5/053

CPC分类号： A61B5/053 ,  A61B5/6821 ,  A61B2562/0215

摘要： The invention provides a method for evaluating a corneal disorder quantitatively and is applicable to living eyes. In particular, the invention provides a method for measuring a corneal transepithelial electric resistance, which method comprises: (1) a step of placing a first electrode on the cornea and a second electrode on the conjunctiva; and (2) a step of flowing an electric current between the first electrode and the second electrode to measure the electric resistance. The invention also provides a device for measuring a corneal transepithelial electric resistance value.

摘要翻译： 本发明提供了一种定量评估角膜障碍并适用于生活眼睛的方法。 特别地，本发明提供了一种测量角膜跨上皮电阻的方法，该方法包括：（1）将第一电极置于角膜上，将第二电极置于结膜上的步骤; 和（2）在第一电极和第二电极之间流动电流以测量电阻的步骤。 本发明还提供了一种用于测量角膜跨上皮电阻值的装置。

公开(公告)号：US08333010B2

公开(公告)日：2012-12-18

申请号：US12936752

申请日：2009-03-30

申请人： Yuzuru Inaba ,  Osamu Okuda ,  Yuji Tanaka ,  Tetsutaro Hachimura

发明人： Yuzuru Inaba ,  Osamu Okuda ,  Yuji Tanaka ,  Tetsutaro Hachimura

IPC分类号： B23P19/00

CPC分类号： H05K13/0465 ,  Y10T29/49828 ,  Y10T29/5137 ,  Y10T29/5313 ,  Y10T29/53178 ,  Y10T29/53183 ,  Y10T29/53187

摘要： In an electronic component mounting apparatus that is used in an electronic component mounting line for producing a mounted substrate by mounting electronic components on a substrate and that subjects the substrate to predetermined operation, a working unit attachment section 30 is provided within a range of movement of a working head, such as a loading head and a paste coating head, wherein a nozzle stocker 9 and a paste trial coating unit 10 can be removably attached as a working unit for performing specific additional operation appropriate for working function of the working head. The nozzle stoker 9 and the paste trial coating unit 10 are attached to the working unit attachment section 30 according to the type of working head.

摘要翻译： 在将电子部件安装在基板上并使基板进行规定的动作的电子部件安装线中使用的电子部件安装装置中，将工作部件安装部30设置在 诸如装载头和糊涂头的工作头，其中喷嘴贮存器9和糊涂试验单元10可移除地附接作为工作单元，用于执行适合于工作头的作业功能的特定附加操作。 根据工作头的种类，将喷嘴加热器9和糊料试
涂单元10安装在作业单元安装部30上。