Invention Grant
- Patent Title: Low power multiplexer with shared, clocked transistor
- Patent Title (中): 具有共享时钟晶体管的低功率多路复用器
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Application No.: US343961Application Date: 1999-06-30
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Publication No.: US6111435APublication Date: 2000-08-29
- Inventor: Jiann-Cherng James Lan , Mahadevamurty Nemani , Narsing K. Vijayrao , Wenjie Jiang , Sudarshan Kumar
- Applicant: Jiann-Cherng James Lan , Mahadevamurty Nemani , Narsing K. Vijayrao , Wenjie Jiang , Sudarshan Kumar
- Applicant Address: CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: CA Santa Clara
- Main IPC: H03K17/693
- IPC: H03K17/693 ; H03K19/173 ; H03K19/20
Abstract:
A circuit includes first and second pull-up transistors having first and second drains, respectively, each coupled to separate voltage clamps. The gates of each of the two pull-up transistors are coupled to a clock signal line. The circuit further includes a shared pull-down transistor, the gate of which is coupled to the clock signal line. The drain of the shared pull-down transistor is coupled to the first drain via at least one pull-down transistor in series with the shared pull-down transistor. The drain of the shared pull-down transistor is also coupled to the second drain via at least one pull-down transistor in series with the shared pull-down transistor. This circuit may be found useful in multiplexing applications.
Public/Granted literature
Information query
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