Invention Grant
- Patent Title: Two signal one power plane circuit board
- Patent Title (中): 两个信号一个电源平面电路板
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Application No.: US09690485Application Date: 2000-10-17
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Publication No.: US06750405B1Publication Date: 2004-06-15
- Inventor: Kenneth Fallon , Miguel A. Jimarez , Ross W. Keesler , John M. Lauffer , Roy H. Magnuson , Voya R. Markovich , Irv Memis , Jim P. Paoletti , Marybeth Perrino , John A. Welsh , William E. Wilson
- Applicant: Kenneth Fallon , Miguel A. Jimarez , Ross W. Keesler , John M. Lauffer , Roy H. Magnuson , Voya R. Markovich , Irv Memis , Jim P. Paoletti , Marybeth Perrino , John A. Welsh , William E. Wilson
- Main IPC: H01R1204
- IPC: H01R1204

Abstract:
A method of forming a printed circuit board or circuit card is provided with a metal layer which serves as a power plane sandwiched between a pair of photoimageable dielectric layers. Photoformed metal filled vias and photoformed plated through holes are in the photopatternable material, and signal circuitry is on the surfaces of each of the dielectric materials and connected to the vias and plated through holes. A border may be around the board or card including a metal layer terminating in from the edge of one of the dielectric layers. A copper foil is provided with clearance holes. First and second layers of photoimageable curable dielectric material is disposed on opposite sides of the copper which are photoimageable material. The patterns are developed on the first and second layers of the photoimageable material to reveal the metal layer through vias. At the clearance holes in the copper, through holes are developed where holes were patterned in both dielectric layers. Thereafter, the surfaces of the photoimageable material, vias and through holes are metalized by copper plating. This is preferably done by protecting the remainder of the circuitry with photoresist and utilizing photolithographic techniques. The photoresist is thereafter removed, leaving a circuit board or card having metalization on both sides, vias extending from both sides to the copper layer in the center, plated through holes connecting the two outer circuitized copper layers.
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