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    Two signal one power plane circuit board
    4.
    发明授权
    Two signal one power plane circuit board 有权
    两个信号一个电源平面电路板

    公开(公告)号：US06204453B1

    公开(公告)日：2001-03-20

    申请号：US09203956

    申请日：1998-12-02

    申请人： Kenneth Fallon ,  Miguel A. Jimarez ,  Ross W. Keesler ,  John M. Lauffer ,  Roy H. Magnuson ,  Voya R. Markovich ,  Irv Memis ,  Jim P. Paoletti ,  Marybeth Perrino ,  John A. Welsh ,  William E. Wilson

    发明人： Kenneth Fallon ,  Miguel A. Jimarez ,  Ross W. Keesler ,  John M. Lauffer ,  Roy H. Magnuson ,  Voya R. Markovich ,  Irv Memis ,  Jim P. Paoletti ,  Marybeth Perrino ,  John A. Welsh ,  William E. Wilson

    IPC分类号： H05K103

    CPC分类号： H05K3/44 ,  H05K1/056 ,  H05K3/0023 ,  H05K3/108 ,  H05K3/426 ,  H05K3/445 ,  H05K2201/09554 ,  H05K2203/0733

    摘要： A method of forming a printed circuit board or circuit card is provided with a metal layer which serves as a power plane sandwiched between a pair of photoimageable dielectric layers. Photoformed metal filled vias and photoformed plated through holes are in the photopatternable material, and signal circuitry is on the surfaces of each of the dielectric materials and connected to the vias and plated through holes. A border may be around the board or card including a metal layer terminating in from the edge of one of the dielectric layers. A copper foil is provided with clearance holes. First and second layers of photoimageable curable dielectric material is disposed on opposite sides of the copper which are photoimageable material. The patterns are developed on the first and second layers of the photoimageable material to reveal the metal layer through vias. At the clearance holes in the copper, through holes are developed where holes were patterned in both dielectric layers. Thereafter, the surfaces of the photoimageable material, vias and through holes are metalized by copper plating. This is preferably done by protecting the remainder of the circuitry with photoresist and utilizing photolithographic techniques. The photoresist is thereafter removed, leaving a circuit board or card having metalization on both sides, vias extending from both sides to the copper layer in the center, plated through holes connecting the two outer circuitized copper layers.

    摘要翻译： 形成印刷电路板或电路卡的方法设置有用作夹在一对可光成像的电介质层之间的电力平面的金属层。 光刻图形金属填充的通孔和光成像的电镀通孔位于光图案化材料中，信号电路位于每个介电材料的表面上，并连接到通孔和电镀通孔。 边界可以在板或卡周围，包括从电介质层之一的边缘终止的金属层。 铜箔上设有间隙孔。 可光成像的可固化介电材料的第一和第二层设置在作为可光成像的材料的铜的相对侧上。 图案在可光成象材料的第一层和第二层上显影，以通过通孔显露金属层。 在铜中的间隙孔处，通孔被开发成在两个电介质层中图案化孔。 此后，可光成像材料，通孔和通孔的表面通过镀铜进行金属化。 这优选通过用光致抗蚀剂和利用光刻技术保护电路的其余部分来实现。 然后去除光致抗蚀剂，留下在两侧具有金属化的电路板或卡，其中心的两侧延伸到铜层，通孔连接两个外部电路化的铜层。

    Composite laminate circuit structure and method of forming the same
    5.
    发明授权
    Composite laminate circuit structure and method of forming the same 有权
    复合层压电路结构及其形成方法

    公开(公告)号：US06175087B1

    公开(公告)日：2001-01-16

    申请号：US09204458

    申请日：1998-12-02

    申请人： Ross W. Keesler ,  Voya R. Markovich ,  Jim P. Paoletti ,  Marybeth Perrino ,  William E. Wilson

    发明人： Ross W. Keesler ,  Voya R. Markovich ,  Jim P. Paoletti ,  Marybeth Perrino ,  William E. Wilson

    IPC分类号： H01R1204

    CPC分类号： H05K3/4641 ,  H05K3/0023 ,  H05K3/429 ,  H05K3/4623 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09809

    摘要： A method forming a composite laminate structure includes providing first and second circuit board element each having circuitry on at least one face thereof and plated through holes. A voltage plane element is provided having at least one voltage plane having opposite faces with layers of partially cured photodielectric material on each face. At least one hole is photopatterned and etched through the voltage plane element but completely isolated from the voltage plane. Each through hole in the voltage plane element is aligned with a plated through hole in each of the circuit board elements to provide a surface on the voltage plane element communicating with the plated through holes. The voltage plane is laminated between the circuit board elements and the photoimageable material on the voltage plane is fully cured. The surfaces of the voltage plane element communicating with the plated through holes in the circuit board elements are plated with a conducting material to establish a connection between the circuitry on the first and second circuit board elements.

    摘要翻译： 形成复合层压结构的方法包括提供在其至少一个表面上具有电路的第一和第二电路板元件，并且通孔穿过。 提供电压平面元件，其具有在每个面上具有与部分固化的光致电介质材料层相对的表面的至少一个电压平面。 至少有一个孔通过电压平面元件进行光刻图案蚀刻，但与电压平面完全隔离。 电压平面元件中的每个通孔与每个电路板元件中的电镀通孔对齐，以在与电镀通孔连通的电压平面元件上提供一个表面。 电压平面层压在电路板元件和电压平面上的可光成像材料之间完全固化。 与电路板元件中的电镀通孔连通的电压平面元件的表面镀有导电材料，以在第一和第二电路板元件之间的电路之间建立连接。

    Composite laminate circuit structure and method of forming the same
    6.
    发明授权
    Composite laminate circuit structure and method of forming the same 有权
    复合层压电路结构及其形成方法

    公开(公告)号：US06451509B2

    公开(公告)日：2002-09-17

    申请号：US09753015

    申请日：2001-01-02

    申请人： Ross W. Keesler ,  Voya R. Markovich ,  Jim P. Paoletti ,  Marybeth Perrino ,  William E. Wilson

    发明人： Ross W. Keesler ,  Voya R. Markovich ,  Jim P. Paoletti ,  Marybeth Perrino ,  William E. Wilson

    IPC分类号： H05K111

    CPC分类号： H05K3/4641 ,  H05K3/0023 ,  H05K3/429 ,  H05K3/4623 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09809

    摘要： A method forming a composite laminate structure includes providing first and second circuit board element each having circuitry on at least one face thereof and plated through holes. A voltage plane element is provided having at least one voltage plane having opposite faces with layers of partially cured photodielectric material on each face. At least one hole is photopatterned and etched through the voltage plane element but completely isolated from the voltage plane. Each through hole in the voltage plane element is aligned with a plated through hole in each of the circuit board elements to provide a surface on the voltage plane element communicating with the plated through holes. The voltage plane is laminated between the circuit board elements and the photoimageable material on the voltage plane is fully cured. The surfaces of the voltage plane element communicating with the plated through holes in the circuit board elements are plated with a conducting material to establish a connection between the circuitry on the first and second circuit board elements.

    摘要翻译： 形成复合层压结构的方法包括提供在其至少一个表面上具有电路的第一和第二电路板元件，并且通孔穿过。 提供电压平面元件，其具有在每个面上具有与部分固化的光致电介质材料层相对的表面的至少一个电压平面。 至少有一个孔通过电压平面元件进行光刻图案蚀刻，但与电压平面完全隔离。 电压平面元件中的每个通孔与每个电路板元件中的电镀通孔对齐，以在与电镀通孔连通的电压平面元件上提供一个表面。 电压平面层压在电路板元件和电压平面上的可光成像材料之间完全固化。 与电路板元件中的电镀通孔连通的电压平面元件的表面镀有导电材料，以在第一和第二电路板元件之间的电路之间建立连接。

    Method for making an encapsulated semiconductor chip module
    8.
    发明授权
    Method for making an encapsulated semiconductor chip module 失效
    制造封装半导体芯片模块的方法

    公开(公告)号：US06558981B2

    公开(公告)日：2003-05-06

    申请号：US09848510

    申请日：2001-05-03

    申请人： Miguel A. Jimarez ,  Marybeth Perrino ,  Son K. Tran ,  Tien Y. Wu

    发明人： Miguel A. Jimarez ,  Marybeth Perrino ,  Son K. Tran ,  Tien Y. Wu

    IPC分类号： H01L2144

    CPC分类号： H01L21/563 ,  H01L23/13 ,  H01L23/3121 ,  H01L2224/73203 ,  H01L2924/3025

    摘要： An encapsulated semiconductor chip module. The chip module has the overlying encapsulant adhered directly and integrally to bare portions of the substrate to which the chip is mounted. This configuration enhances the adhesion and inhibits unintended delamination of the encapsulant from the balance of the module. The module is made by patterning anchor openings into the solder mask. The anchor openings expose corresponding portions of the substrate. It is important to locate the anchor openings over parts of the substrate that do not have circuitry on them, that is, on bare portions, so as to avoid corrosion or contamination of the circuit connections.

    摘要翻译： 封装的半导体芯片模块。 芯片模块具有直接并整体地粘附到芯片所安装的基板的裸露部分的上覆密封剂。 这种构造增强了粘附性，并且阻止了封装材料与模块平衡的意外分层。 该模块通过将锚定开口图案图案化成焊接掩模。 锚定开口露出衬底的相应部分。 重要的是将锚定开口定位在其上没有电路的基板的部分上，即在裸露的部分上，以避免腐蚀或电路连接的污染。

    Encapsulated chip module and method of making same
    9.
    发明授权
    Encapsulated chip module and method of making same 失效
    封装的半导体模块

    公开(公告)号：US06246124B1

    公开(公告)日：2001-06-12

    申请号：US09154618

    申请日：1998-09-16

    申请人： Miguel A. Jimarez ,  Marybeth Perrino ,  Son K. Tran ,  Tien Y. Wu

    发明人： Miguel A. Jimarez ,  Marybeth Perrino ,  Son K. Tran ,  Tien Y. Wu

    IPC分类号： H01L2329

    CPC分类号： H01L21/563 ,  H01L23/13 ,  H01L23/3121 ,  H01L2224/73203 ,  H01L2924/3025

    摘要： An encapsulated semiconductor chip module. The chip module has the overlying encapsulant adhered directly and integrally to bare portions of the substrate to which the chip is mounted. This configuration enhances the adhesion and inhibits unintended delamination of the encapsulant from the balance of the module. The module is made by patterning anchor openings into the solder mask. The anchor openings expose corresponding portions of the substrate. It is important to locate the anchor openings over parts of the substrate that do not have circuitry on them, that is, on bare portions, so as to avoid corrosion or contamination of the circuit connections.

    摘要翻译： 封装的半导体芯片模块。 芯片模块具有直接并整体地粘附到芯片所安装的基板的裸露部分的上覆密封剂。 这种构造增强了粘附性，并且阻止了封装材料与模块平衡的意外分层。 该模块通过将锚定开口图案图案化成焊接掩模。 锚定开口露出衬底的相应部分。 重要的是将锚定开口定位在其上没有电路的基板的部分上，即在裸露的部分上，以避免腐蚀或电路连接的污染。