发明授权
- 专利标题： Semiconductor integrated circuit with reduced leakage current
- 专利标题（中）： 具有减小漏电流的半导体集成电路
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申请号： US10342045申请日： 2003-01-14
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公开(公告)号： US06861882B2公开(公告)日： 2005-03-01
- 发明人: Toshiyuki Furusawa , Daisuke Sonoda , Kimiyoshi Usami , Naoyuki Kawabe , Masayuki Koizumi , Hidemasa Zama , Masahiro Kanazawa
- 申请人： Toshiyuki Furusawa , Daisuke Sonoda , Kimiyoshi Usami , Naoyuki Kawabe , Masayuki Koizumi , Hidemasa Zama , Masahiro Kanazawa
- 申请人地址： JP Tokyo
- 专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人地址： JP Tokyo
- 代理机构： Frommer Lawrence & Haug LLP
- 优先权： JP2000-295234 20000927
- 主分类号： H01L21/822
- IPC分类号： H01L21/822 ; H01L27/04 ; H03K19/00 ; H03L7/00
摘要：
A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.
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