发明授权
US06922070B2 Evaluating pattern for measuring an erosion of a semiconductor wafer polished by a chemical mechanical polishing
有权
用于测量通过化学机械抛光抛光的半导体晶片的侵蚀的评估图案
- 专利标题： Evaluating pattern for measuring an erosion of a semiconductor wafer polished by a chemical mechanical polishing
- 专利标题（中）： 用于测量通过化学机械抛光抛光的半导体晶片的侵蚀的评估图案
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申请号： US10834063申请日： 2004-04-29
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公开(公告)号： US06922070B2公开(公告)日： 2005-07-26
- 发明人: Tadashi Narita
- 申请人： Tadashi Narita
- 申请人地址： JP Tokyo
- 专利权人： Oki Electric Industry Co., Ltd.
- 当前专利权人： Oki Electric Industry Co., Ltd.
- 当前专利权人地址： JP Tokyo
- 代理机构： Volentine Francos & Whitt, PLLC
- 优先权： JP2000-288451 20000922
- 主分类号： B60B9/12
- IPC分类号： B60B9/12 ; B24B37/04 ; B24B49/10 ; B60B9/14 ; G01R31/28 ; H01L21/304 ; H01L21/3205 ; H01L21/66 ; H01L21/768 ; H01L23/52 ; H01L23/522 ; H01L23/544 ; G01R31/26 ; H01L21/4763
摘要：
An evaluating pattern includes a conductive pattern formed on a substrate, an insulating layer which is formed on the conductive pattern, a plurality of contact holes formed in a rectangular area through the insulating layer, and a conductive material filled into the contact holes to the conductive pattern.
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