Invention Grant
- Patent Title: Method and apparatus to generate a reference value in a memory array
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Application No.: US10740551Application Date: 2003-12-22
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Publication No.: US06952376B2Publication Date: 2005-10-04
- Inventor: Dinesh Somasekhar , Yibin Ye , Muhammad M. Khellah , Fabrice Paillet , Stephen H. Tang , Ali Keshavarzi , Shih-Lien Lu , Vivek K. De
- Applicant: Dinesh Somasekhar , Yibin Ye , Muhammad M. Khellah , Fabrice Paillet , Stephen H. Tang , Ali Keshavarzi , Shih-Lien Lu , Vivek K. De
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Fleshner & Kim, LLP
- Main IPC: G11C7/14
- IPC: G11C7/14 ; G11C7/18 ; G11C11/4097 ; G11C11/4099 ; G11C7/02
Abstract:
An apparatus and method for generating a reference in a memory circuit are disclosed. At least two dummy bit-cells are used to generate a reference voltage. One cell has high value stored and the other has a low value stored. The cells are activated and discharged into respective bit-lines. The bit-lines are equalized during the discharge process to generate a reference that is approximately a mid point between a high value cell and a low value cell.
Public/Granted literature
- US20050135169A1 Method and apparatus to generate a reference value in a memory array Public/Granted day:2005-06-23
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