Invention Grant
- Patent Title: Semiconductor package with through silicon vias
- Patent Title (中): 半导体封装通过硅通孔
-
Application No.: US12897124Application Date: 2010-10-04
-
Publication No.: US08946742B2Publication Date: 2015-02-03
- Inventor: Chen-Hua Yu , Hung-Pin Chang , Yung-Chi Lin , Chia-Lin Yu , Jui-Pin Hung , Chien Ling Hwang
- Applicant: Chen-Hua Yu , Hung-Pin Chang , Yung-Chi Lin , Chia-Lin Yu , Jui-Pin Hung , Chien Ling Hwang
- Applicant Address: TW Hsinchu
- Assignee: TSMC Solid State Lighting Ltd.
- Current Assignee: TSMC Solid State Lighting Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L33/00
- IPC: H01L33/00 ; H01L21/768 ; H01L21/683 ; H01L23/48 ; H01L33/48 ; H01L33/64 ; H01L21/48 ; H01L23/14 ; H01L23/498 ; H01L23/00 ; H01L33/62

Abstract:
The substrate with through silicon plugs (or vias) described above removes the need for conductive bumps. The process flow is very simple and cost efficient. The structures described combines the separate TSV, redistribution layer, and conductive bump structures into a single structure. By combining the separate structures, a low resistance electrical connection with high heat dissipation capability is created. In addition, the substrate with through silicon plugs (or vias, or trenches) also allows multiple chips to be packaged together. A through silicon trench can surround the one or more chips to provide protection against copper diffusing to neighboring devices during manufacturing. In addition, multiple chips with similar or different functions can be integrated on the TSV substrate. Through silicon plugs with different patterns can be used under a semiconductor chip(s) to improve heat dissipation and to resolve manufacturing concerns.
Public/Granted literature
- US20110241040A1 NOVEL SEMICONDUCTOR PACKAGE WITH THROUGH SILICON VIAS Public/Granted day:2011-10-06
Information query
IPC分类: