Invention Grant
- Patent Title: Overlay abnormality gating by Z data
- Patent Title (中): 叠加异常门控Z数据
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Application No.: US13940335Application Date: 2013-07-12
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Publication No.: US09123583B2Publication Date: 2015-09-01
- Inventor: Chun-Hsien Lin , Kuo-Hung Chao , Yi-Ping Hsieh , Yen-Di Tsen , Jui-Chun Peng , Heng-Hsin Liu , Jong-I Mou
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Associates, LLC
- Main IPC: G01N21/00
- IPC: G01N21/00 ; H01L21/66 ; G01N21/95 ; G03F7/00 ; G01B13/06 ; G01B11/24

Abstract:
The present disclosure relates to a method of monitoring wafer topography. A position and orientation of a plurality first alignment shapes disposed on a surface of a wafer are measured. Wafer topography as a function of wafer position is modeled by subjecting the wafer to an alignment which simultaneously minimizes misalignment between the wafer and a patterning apparatus and maximizes a focus of radiation on the surface. A non-correctable error is determined as a difference between the modeled wafer topography and a measured wafer topography. A maximum non-correctable error per field is determined for a wafer, and a mean variation in the maximum non-correctable error across each field within each wafer of a lot is determined, both within a layer and across layers. These values are then verified against a set of statistical process control rules to determine if they are within a specification limit of the manufacturing process.
Public/Granted literature
- US20150015870A1 Overlay Abnormality Gating by Z Data Public/Granted day:2015-01-15
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