Lithography system and methods
    1.
    发明授权

    公开(公告)号:US12287572B2

    公开(公告)日:2025-04-29

    申请号:US17232483

    申请日:2021-04-16

    Abstract: A method includes: depositing a mask layer over a substrate; directing first radiation reflected from a central collector section of a sectional collector of a lithography system toward the mask layer according to a pattern; directing second radiation reflected from a peripheral collector section of the sectional collector toward the mask layer according to the pattern, wherein the peripheral collector section is vertically separated from the central collector section by a gap; forming openings in the mask layer by removing first regions of the mask layer exposed to the first radiation and second regions of the mask layer exposed to the second radiation; and removing material of a layer underlying the mask layer exposed by the openings.

    Overlay Abnormality Gating by Z Data
    10.
    发明申请
    Overlay Abnormality Gating by Z Data 有权
    叠加异常门控Z数据

    公开(公告)号:US20150015870A1

    公开(公告)日:2015-01-15

    申请号:US13940335

    申请日:2013-07-12

    Abstract: The present disclosure relates to a method of monitoring wafer topography. A position and orientation of a plurality first alignment shapes disposed on a surface of a wafer are measured. Wafer topography as a function of wafer position is modeled by subjecting the wafer to an alignment which simultaneously minimizes misalignment between the wafer and a patterning apparatus and maximizes a focus of radiation on the surface. A non-correctable error is determined as a difference between the modeled wafer topography and a measured wafer topography. A maximum non-correctable error per field is determined for a wafer, and a mean variation in the maximum non-correctable error across each field within each wafer of a lot is determined, both within a layer and across layers. These values are then verified against a set of statistical process control rules to determine if they are within a specification limit of the manufacturing process.

    Abstract translation: 本公开涉及一种监测晶片形貌的方法。 测量设置在晶片表面上的多个第一对准形状的位置和取向。 作为晶片位置的函数的晶片形貌通过使晶片经受对准,同时最小化晶片和图案形成装置之间的未对准并使辐射在表面上的焦点最大化来建模。 不可校正误差被确定为模拟晶片形貌与测量的晶片形貌之间的差异。 对于晶片确定每场的最大不可校正误差,并且在层内和跨层中确定在批次的每个晶片内的每个场上的每个场的最大不可校正误差的平均变化。 然后根据一组统计过程控制规则验证这些值,以确定它们是否在制造过程的规格限制内。

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