-
Patent Agency Ranking
公开(公告)号：US20150015870A1
公开(公告)日：2015-01-15
申请号：US13940335
申请日：2013-07-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chun-Hsien Lin , Kuo-Hung Chao , Yi-Ping Hsieh , Yen-Di Tsen , Jui-Chun Peng , Heng-Hsin Liu , Jong-I Mou
CPC classification number: H01L22/12 , G01B11/24 , G01B13/065 , G01B2210/56 , G01N21/9501 , G03F7/00 , G03F7/70533 , G03F9/7003 , H01L22/20 , H01L22/30
Abstract: The present disclosure relates to a method of monitoring wafer topography. A position and orientation of a plurality first alignment shapes disposed on a surface of a wafer are measured. Wafer topography as a function of wafer position is modeled by subjecting the wafer to an alignment which simultaneously minimizes misalignment between the wafer and a patterning apparatus and maximizes a focus of radiation on the surface. A non-correctable error is determined as a difference between the modeled wafer topography and a measured wafer topography. A maximum non-correctable error per field is determined for a wafer, and a mean variation in the maximum non-correctable error across each field within each wafer of a lot is determined, both within a layer and across layers. These values are then verified against a set of statistical process control rules to determine if they are within a specification limit of the manufacturing process.
Abstract translation: 本公开涉及一种监测晶片形貌的方法。 测量设置在晶片表面上的多个第一对准形状的位置和取向。 作为晶片位置的函数的晶片形貌通过使晶片经受对准，同时最小化晶片和图案形成装置之间的未对准并使辐射在表面上的焦点最大化来建模。 不可校正误差被确定为模拟晶片形貌与测量的晶片形貌之间的差异。 对于晶片确定每场的最大不可校正误差，并且在层内和跨层中确定在批次的每个晶片内的每个场上的每个场的最大不可校正误差的平均变化。 然后根据一组统计过程控制规则验证这些值，以确定它们是否在制造过程的规格限制内。
-
公开(公告)号：US09811000B2
公开(公告)日：2017-11-07
申请号：US14929098
申请日：2015-10-30
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Chia-Feng Liao , Chun-Hsien Lin , Pei-Yi Su , Yi-Ming Dai , Chung-Hsing Lee , Chien-Ko Liao , Chun-Yung Chang , Nan-Jung Chen , Pei-Yuan Wu , Hsien-Mao Huang
CPC classification number: G03F7/70483 , G01N21/8851 , G01N21/9501 , H01L21/67253 , H01L21/67259 , H01L22/12
Abstract: A photolithography tool includes at least one process chamber, at least one front opening unified pod (FOUP) stage, at least one moving mechanism, and an image sensor. The moving mechanism is configured to move the wafer from the process chamber to the FOUP stage. The image sensor is configured to capture the image of the wafer on the moving mechanism.
-
公开(公告)号：US09158867B2
公开(公告)日：2015-10-13
申请号：US13647643
申请日：2012-10-09
Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.
Inventor： Chun-Hsien Lin , Jui-Long Chen , Hui-Yun Chao , Jong-I Mou , Chin-Hsiang Lin
CPC classification number: G06F17/50 , G03F7/70533 , G03F7/70616 , G05B23/024
Abstract: A method for analyzing abnormalities in a semiconductor processing system provides performing an analysis of variance on a production history associated with each of a plurality of tools at each of a plurality of process steps for each of a plurality of processed wafers, and key process steps are identified. A regression analysis on a plurality of measurements of the plurality of wafers at each process step is performed and key measurement parameters are identified. An analysis of covariance on the key measurement parameters and key process steps, and the key process steps are ranked based on an f-ratio, therein ranking an abnormality of the key process steps. Further, the plurality of tools associated with each of the key process steps are ranked based on an orthogonal t-ratio associated with an analysis of covariance, therein ranking an abnormality each tool associated with the key process steps.
Abstract translation: 一种用于分析半导体处理系统中的异常的方法，提供了在多个处理晶片中的每一个的多个处理步骤中的每一个处执行与多个工具中的每一个相关联的生产历史上的方差分析，并且关键处理步骤 确定。 执行在每个处理步骤对多个晶片的多个测量的回归分析，并且识别关键测量参数。 关键测量参数和关键过程步骤的协方差分析以及关键过程步骤基于f比进行排序，其中排列关键过程步骤的异常。 此外，与关键处理步骤中的每一个相关联的多个工具基于与协方差分析相关联的正交t比进行排序，其中对与关键处理步骤相关联的每个工具进行排序。
-
公开(公告)号：US20140100684A1
公开(公告)日：2014-04-10
申请号：US13647643
申请日：2012-10-09
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.
Inventor： Chun-Hsien Lin , Jui-Long Chen , Hui-Yun Chao , Jong-I Mou , Chin-Hsiang Lin
IPC: G06F19/00
CPC classification number: G06F17/50 , G03F7/70533 , G03F7/70616 , G05B23/024
Abstract: A method for analyzing abnormalities in a semiconductor processing system provides performing an analysis of variance on a production history associated with each of a plurality of tools at each of a plurality of process steps for each of a plurality of processed wafers, and key process steps are identified. A regression analysis on a plurality of measurements of the plurality of wafers at each process step is performed and key measurement parameters are identified. An analysis of covariance on the key measurement parameters and key process steps, and the key process steps are ranked based on an f-ratio, therein ranking an abnormality of the key process steps. Further, the plurality of tools associated with each of the key process steps are ranked based on an orthogonal t-ratio associated with an analysis of covariance, therein ranking an abnormality each tool associated with the key process steps.
Abstract translation: 一种用于分析半导体处理系统中的异常的方法，提供了在多个处理晶片中的每一个的多个处理步骤中的每一个处执行与多个工具中的每一个相关联的生产历史上的方差分析，并且关键处理步骤 确定。 执行在每个处理步骤对多个晶片的多个测量的回归分析，并且识别关键测量参数。 关键测量参数和关键过程步骤的协方差分析以及关键过程步骤基于f比进行排序，其中排列关键过程步骤的异常。 此外，与关键处理步骤中的每一个相关联的多个工具基于与协方差分析相关联的正交t比进行排序，其中对与关键处理步骤相关联的每个工具进行排序。
-
公开(公告)号：US09123583B2
公开(公告)日：2015-09-01
申请号：US13940335
申请日：2013-07-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chun-Hsien Lin , Kuo-Hung Chao , Yi-Ping Hsieh , Yen-Di Tsen , Jui-Chun Peng , Heng-Hsin Liu , Jong-I Mou
CPC classification number: H01L22/12 , G01B11/24 , G01B13/065 , G01B2210/56 , G01N21/9501 , G03F7/00 , G03F7/70533 , G03F9/7003 , H01L22/20 , H01L22/30
Abstract: The present disclosure relates to a method of monitoring wafer topography. A position and orientation of a plurality first alignment shapes disposed on a surface of a wafer are measured. Wafer topography as a function of wafer position is modeled by subjecting the wafer to an alignment which simultaneously minimizes misalignment between the wafer and a patterning apparatus and maximizes a focus of radiation on the surface. A non-correctable error is determined as a difference between the modeled wafer topography and a measured wafer topography. A maximum non-correctable error per field is determined for a wafer, and a mean variation in the maximum non-correctable error across each field within each wafer of a lot is determined, both within a layer and across layers. These values are then verified against a set of statistical process control rules to determine if they are within a specification limit of the manufacturing process.
Abstract translation: 本公开涉及一种监测晶片形貌的方法。 测量设置在晶片表面上的多个第一对准形状的位置和取向。 作为晶片位置的函数的晶片形貌通过使晶片经受对准，同时最小化晶片和图案形成装置之间的未对准并使辐射在表面上的焦点最大化来建模。 不可校正误差被确定为模拟晶片形貌与测量的晶片形貌之间的差异。 对于晶片确定每场的最大不可校正误差，并且在层内和跨层中确定在批次的每个晶片内的每个场上的每个场的最大不可校正误差的平均变化。 然后根据一组统计过程控制规则验证这些值，以确定它们是否在制造过程的规格限制内。
-
-
-
-
Search Results
5
records
(took 0.016 seconds)
