Invention Grant
- Patent Title: Process design to improve transistor variations and performance
- Patent Title (中): 工艺设计,以提高晶体管的变化和性能
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Application No.: US14156515Application Date: 2014-01-16
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Publication No.: US09224814B2Publication Date: 2015-12-29
- Inventor: Tsung-Hsing Yu , Chia-Wen Liu , Yeh Hsu , Shih-Syuan Huang , Ken-Ichi Goto , Zhiqiang Wu
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Associates, LLC
- Main IPC: H01L29/08
- IPC: H01L29/08 ; H01L29/78 ; H01L29/66 ; H01L21/306 ; H01L21/265 ; H01L21/02 ; H01L29/16

Abstract:
The present disclosure relates to a method of forming a transistor device having a carbon implantation region that provides for a low variation of voltage threshold, and an associated apparatus. The method is performed by forming a well region within a semiconductor substrate. The semiconductor substrate is selectively etched to form a recess within the well region. After formation of the recess, a carbon implantation is selectively performed to form a carbon implantation region within the semiconductor substrate at a position underlying the recess. An epitaxial growth is then performed to form one or more epitaxial layers within the recess at a position overlying the carbon implantation region. Source and drain regions are subsequently formed within the semiconductor substrate such that a channel region, comprising the one or more epitaxial layers, separates the source/drains from one another.
Public/Granted literature
- US20150200296A1 PROCESS DESIGN TO IMPROVE TRANSISTOR VARIATIONS AND PERFORMANCE Public/Granted day:2015-07-16
Information query
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