In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a plurality of graphics engines each to independently perform graphics operations; and, a power control unit coupled to the plurality of cores to control power consumption of the processor, where the power control unit includes a power excursion control logic to limit a power consumption level of the processor from being above a defined power limit for more than a duty cycle portion of an operating period. Other embodiments are described and claimed.