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公开(公告)号：US10963031B2
公开(公告)日：2021-03-30
申请号：US15906960
申请日：2018-02-27
申请人： INTEL CORPORATION
IPC分类号： G06F1/3206 , H04B3/54 , H04B3/56 , G06F1/3209 , G06F1/26 , H04H20/38 , H04L12/863
摘要： A server system includes a common power bus, a power supply to provide direct current (DC) power through the common power bus, at least one node including a processor to receive the DC power through the common power bus, a transmitter capacitive coupled to the common power bus to transmit a power information signal from the power supply through the common power bus, and at least one receiver capacitive coupled to the common power bus to receive the power information signal transmitted by the transmitter and to provide the received power information signal to the at least one node. A plurality of buffers respectively coupled between the common power bus and each of the power supply and the at least one node provide path separation for high frequency and low frequency currents.
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公开(公告)号：US10719107B2
公开(公告)日：2020-07-21
申请号：US15084374
申请日：2016-03-29
申请人： Intel Corporation
发明人： Justin J. Song , Devadatta V. Bodas , Muralidhar Rajappa , Brian J. Griffith , Andy Hoffman , Gopal R. Mundada
IPC分类号： G06F1/00 , G06F1/26 , G06F1/3206
摘要： A method and apparatus for node power regulation among nodes that share a power supply are described. In one embodiment, the apparatus comprises a power supply unit to provide input power and a plurality of nodes coupled to receive the input power, where each node of the plurality of nodes is operable to run power management logic, and wherein two or more nodes of the plurality of nodes alternate between performing power management and providing power regulation control information to other nodes of the plurality of nodes to regulate power consumption by the plurality of nodes, with, at any one time, only one node of plurality of nodes generating the power regulation control to regulate power for the plurality of nodes.
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3.发明申请公开(公告)号：US20170185132A1
公开(公告)日：2017-06-29
申请号：US14757903
申请日：2015-12-23
申请人： Intel Corporation
发明人： Devadatta Bodas , Meenakshi Arunachalam , Ilya Sharapov , Charles R. Yount , Scott B. Huck , Ramakrishna Huggahalli , Justin J. Song , Brian J. Griffith , Muralidhar Rajappa , Lingdan (Linda) Zeng
CPC分类号： G06F1/3206 , G06F1/324 , G06F11/3428 , Y02D10/126
摘要： A method of assessing energy efficiency of a High-performance computing (HPC) system, including: selecting a plurality of HPC workloads to run on a system under test (SUT) with one or more power constraints, wherein the SUT includes a plurality of HPC nodes in the HPC system, executing the plurality of HPC workloads on the SUT, and generating a benchmark metric for the SUT based on a baseline configuration for each selected HPC workload and a plurality of measured performance per power values for each executed workload at each selected power constraint is shown.
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公开(公告)号：US10037075B2
公开(公告)日：2018-07-31
申请号：US15089489
申请日：2016-04-02
申请人： INTEL CORPORATION
CPC分类号： G06F1/3296 , G06F1/26 , G06F1/263 , G06F1/305 , H02J7/00 , H02M3/04 , Y02D10/172
摘要： Voltage regulation techniques for electronic devices are described. In one embodiment, for example, an apparatus may comprise an electronic element comprising one or more integrated circuits, a voltage regulator to regulate an input voltage of the electronic element, the voltage regulator to source an output current comprising at least a portion of an input current of the electronic element, the voltage regulator to operate in a current-limiting mode to limit the output current when the input current exceeds a threshold current, and a capacitor bank comprising one or more capacitors, the capacitor bank to source a supplemental current to supplement the output current of the voltage regulator when the voltage regulator operates in the current-limiting mode. Other embodiments are described and claimed.
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5.发明申请公开(公告)号：US20170285702A1
公开(公告)日：2017-10-05
申请号：US15084374
申请日：2016-03-29
申请人： Intel Corporation
发明人： Justin J. Song , Devadatta V. Bodas , Muralidhar Rajappa , Brian J. Griffith , Andy Hoffman , Gopal R. Mundada
IPC分类号： G06F1/26
摘要： A method and apparatus for node power regulation among nodes that share a power supply are described. In one embodiment, the apparatus comprises a power supply unit to provide input power and a plurality of nodes coupled to receive the input power, where each node of the plurality of nodes is operable to run power management logic, and wherein two or more nodes of the plurality of nodes alternate between performing power management and providing power regulation control information to other nodes of the plurality of nodes to regulate power consumption by the plurality of nodes, with, at any one time, only one node of plurality of nodes generating the power regulation control to regulate power for the plurality of nodes.
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公开(公告)号：US10564709B2
公开(公告)日：2020-02-18
申请号：US16049779
申请日：2018-07-30
申请人： INTEL CORPORATION
IPC分类号： G06F1/3296 , G06F1/26 , G06F1/30 , H02M3/04 , H02J7/00
摘要： Voltage regulation techniques for electronic devices are described. In one embodiment, for example, an apparatus may comprise an electronic element comprising one or more integrated circuits, a voltage regulator to regulate an input voltage of the electronic element, the voltage regulator to source an output current comprising at least a portion of an input current of the electronic element, the voltage regulator to operate in a current-limiting mode to limit the output current when the input current exceeds a threshold current, and a capacitor bank comprising one or more capacitors, the capacitor bank to source a supplemental current to supplement the output current of the voltage regulator when the voltage regulator operates in the current-limiting mode. Other embodiments are described and claimed.
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公开(公告)号：US09846463B2
公开(公告)日：2017-12-19
申请号：US13631824
申请日：2012-09-28
申请人： Intel Corporation
发明人： Krishnakanth Sistla , Martin Mark Rowland , Efraim Rotem , Brian J. Griffith , Ankush Varma , Anupama Suryanarayanan
CPC分类号： G06F1/26 , G06F1/3203 , G06F1/3243 , G06F1/329 , Y02D10/152 , Y02D10/24
摘要： A processor is described that includes a quick signal path from an input of the processor to logic circuitry within the processor. The input is to receive a fast throttle down signal. The logic circuitry is to throttle down a rate at which the processor issues instructions for execution in response to the fast throttle down signal. The quick signal path is to impose practicably minimal propagation delay of the fast throttle down signal within the processor.
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公开(公告)号：US20160380675A1
公开(公告)日：2016-12-29
申请号：US15258803
申请日：2016-09-07
申请人： INTEL CORPORATION
IPC分类号： H04B3/54 , H04H20/38 , H04L12/863
CPC分类号： G06F1/3206 , G06F1/26 , G06F1/3209 , H04B3/546 , H04B3/548 , H04B3/56 , H04B2203/547 , H04B2203/5483 , H04B2203/5495 , H04H20/38 , H04L47/50 , Y04S40/146
摘要： A server system includes a common power bus, a power supply to provide direct current (DC) power through the common power bus, at least one node including a processor to receive the DC power through the common power bus, a transmitter capacitive coupled to the common power bus to transmit a power information signal from the power supply through the common power bus, and at least one receiver capacitive coupled to the common power bus to receive the power information signal transmitted by the transmitter and to provide the received power information signal to the at least one node. A plurality of buffers respectively coupled between the common power bus and each of the power supply and the at least one node provide path separation for high frequency and low frequency currents.
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公开(公告)号：US09461709B2
公开(公告)日：2016-10-04
申请号：US14319485
申请日：2014-06-30
申请人： INTEL CORPORATION
CPC分类号： G06F1/3206 , G06F1/26 , G06F1/3209 , H04B3/546 , H04B3/548 , H04B3/56 , H04B2203/547 , H04B2203/5483 , H04B2203/5495 , H04H20/38 , H04L47/50 , Y04S40/146
摘要： A server system includes a common power bus, a power supply to provide direct current (DC) power through the common power bus, at least one node including a processor to receive the DC power through the common power bus, a transmitter capacitive coupled to the common power bus to transmit a power information signal from the power supply through the common power bus, and at least one receiver capacitive coupled to the common power bus to receive the power information signal transmitted by the transmitter and to provide the received power information signal to the at least one node. A plurality of buffers respectively coupled between the common power bus and each of the power supply and the at least one node provide path separation for high frequency and low frequency currents.
摘要翻译： 服务器系统包括公用电源总线，用于通过公共电源总线提供直流（DC）电力的电源，至少一个节点，其包括处理器以通过公共电源总线接收DC电力;发射机电容耦合到 公共电源总线，用于通过公共电源总线从电源传输电力信息信号;以及至少一个接收器，电容耦合到公共电力总线，以接收由发射机发送的电力信息信号，并将接收到的功率信息信号提供给 该至少一个节点。 分别耦合在公共电源总线与电源和至少一个节点中的每一个的多个缓冲器为高频和低频电流提供路径间隔。
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公开(公告)号：US10429912B2
公开(公告)日：2019-10-01
申请号：US15846161
申请日：2017-12-18
申请人： Intel Corporation
发明人： Krishnakanth Sistla , Martin Rowland , Efraim Rotem , Brian J. Griffith , Ankush Varma , Anupama Suryanarayanan
IPC分类号： G06F1/26 , G06F1/329 , G06F1/3203 , G06F1/3234
摘要： A processor is described that includes a quick signal path from an input of the processor to logic circuitry within the processor. The input is to receive a fast throttle down signal. The logic circuitry is to throttle down a rate at which the processor issues instructions for execution in response to the fast throttle down signal. The quick signal path is to impose practicably minimal propagation delay of the fast throttle down signal within the processor.
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