公开(公告)号：US09268393B2

公开(公告)日：2016-02-23

申请号：US13997295

申请日：2012-11-30

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Krishnakanth Sistla ,  Martin T. Rowland ,  Brian J. Griffith ,  Viktor D. Vogman ,  Joseph R. Doucette ,  Eric J. Dehaemer ,  Vivek Garg ,  Chris Poirier ,  Jeremy J. Shrall ,  Avinash N. Ananthakrishnan ,  Stephen H. Gunther

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/06 ,  G06F9/45

CPC classification number: G06F1/3234 ,  G06F1/06 ,  G06F1/324 ,  G06F8/4432 ,  Y02D10/126

Abstract: In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a plurality of graphics engines each to independently perform graphics operations; and, a power control unit coupled to the plurality of cores to control power consumption of the processor, where the power control unit includes a power excursion control logic to limit a power consumption level of the processor from being above a defined power limit for more than a duty cycle portion of an operating period. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括多个核心，每个核心各自独立地执行指令，多个图形引擎各自独立地执行图形操作; 以及功率控制单元，其耦合到所述多个核以控制所述处理器的功率消耗，其中所述功率控制单元包括功率偏移控制逻辑，以将所述处理器的功率消耗水平限制在高于限定功率极限以上 工作周期的占空比部分。 描述和要求保护其他实施例。