Invention Grant
- Patent Title: Self-aligned liner method of avoiding PL gate damage
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Application No.: US14672777Application Date: 2015-03-30
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Publication No.: US09287285B2Publication Date: 2016-03-15
- Inventor: Fang-Hao Hsu , Zusing Yang , Hong-Ji Lee
- Applicant: Macronix International Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: MACRONIX INTERNATIONAL CO., LTD.
- Current Assignee: MACRONIX INTERNATIONAL CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Stout, Uxa & Buyan, LLP
- Agent Frank J. Uxa
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L27/115 ; H01L29/40 ; H01L21/8238 ; H01L21/28 ; H01L29/423 ; H01L29/06 ; H01L29/49 ; H01L29/51
Abstract:
A self-align method of preparing semiconductor gates for formation of a silicide, such as a cobalt silicide (CoSi) layer, is disclosed. Deposition of silicon nitride (SiN) and low-temperature oxide (LTO) liner types, the SiN liner having an overhang structure, prevent damage to the gates while forming a self-aligned source. The undamaged gates are suitable for CoSi deposition.
Public/Granted literature
- US20150228661A1 SELF-ALIGNED LINER METHOD OF AVOIDING PL GATE DAMAGE Public/Granted day:2015-08-13
Information query
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