公开(公告)号：US09224803B2

公开(公告)日：2015-12-29

申请号：US13875998

申请日：2013-05-02

Applicant: Macronix International Co., Ltd.

Inventor： Zusing Yang ,  Fang-Hao Hsu ,  Hong-Ji Lee

IPC: H01L23/58 ,  H01L29/06 ,  H01L23/485 ,  H01L21/768

CPC classification number: H01L29/06 ,  H01L21/76816 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A small contact hole having a large aspect ratio is formed by employing a stop layer with a trench formed therein. A relatively large contact hole is formed above the trench, and the small contact hole is formed below the trench, using properties of the trench and the stop layer to limit the size of the small contact hole.

Abstract translation: 通过使用其中形成有沟槽的阻挡层形成具有大纵横比的小接触孔。 在沟槽上方形成较大的接触孔，并利用沟槽和阻挡层的特性形成小沟槽下方的小接触孔，以限制小接触孔的尺寸。

公开(公告)号：US20150214054A1

公开(公告)日：2015-07-30

申请号：US14162737

申请日：2014-01-24

Applicant: Macronix International Co., Ltd.

Inventor： Zusing Yang ,  Hong-Ji Lee

IPC: H01L21/16 ,  H01L21/027 ,  H01L21/02

CPC classification number: H01L21/165 ,  H01L21/02063 ,  H01L21/02068 ,  H01L21/02568 ,  H01L21/02614 ,  H01L21/02639 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/321 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76849

Abstract: Effects of copper oxide formation in semiconductor manufacture are mitigated by etching with sulfide plasmas. The plasmas form protective copper sulfide films on copper surfaces and prevent copper oxide formation. When copper oxide formation does occur, the sulfide plasmas are able to transform the copper oxide into acceptable or more conductive copper compounds. Non-oxide copper compounds are removed using clear wet strips.

Abstract translation: 半导体制造中氧化铜形成的影响通过用硫化物等离子体蚀刻来缓解。 等离子体在铜表面形成保护性硫化铜膜，防止形成铜氧化物。 当发生铜氧化物形成时，硫化物等离子体能够将氧化铜转化为可接受或更导电的铜化合物。 使用清晰的湿条除去非氧化物铜化合物。

公开(公告)号：US11004863B2

公开(公告)日：2021-05-11

申请号：US16557803

申请日：2019-08-30

Applicant: MACRONIX International Co., Ltd.

Inventor： Zusing Yang

IPC: H01L27/11582 ,  H01L29/786 ,  H01L29/423 ,  H01L21/311 ,  H01L27/1157

Abstract: A non-volatile memory having a gate all around thin film transistor includes a multi-layer structure, an elongated plug structure, a first conductive plug, and a second conductive plug. The multi-layer structure includes a plurality of gate electrode layers stacked on a substrate separately from each other. The elongated plug structure penetrates through the multi-layer structure, and a cross-section of the elongated plug structure has an elongated contour. The elongated plug structure includes an insulating pillar, a channel layer, and a gate dielectric layer. The channel layer surrounds the insulating pillar. The gate dielectric layer surrounds the channel layer. The gate electrode layers surround the gate dielectric layer. The first conductive plug is disposed between the channel layer and the substrate and between the insulating pillar and the substrate. The second conductive plug is disposed on the insulating pillar and is covered by the channel layer.

公开(公告)号：US09012282B2

公开(公告)日：2015-04-21

申请号：US13942490

申请日：2013-07-15

Applicant: Macronix International Co., Ltd.

Inventor： Fang-Hao Hsu ,  Zusing Yang ,  Hong-Ji Lee

IPC: H01L23/48 ,  H01L29/40 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/28 ,  H01L29/423 ,  H01L27/115

CPC classification number: H01L27/11568 ,  H01L21/28273 ,  H01L21/823835 ,  H01L27/11521 ,  H01L29/0684 ,  H01L29/401 ,  H01L29/42324 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/518 ,  H01L29/78

Abstract: A self-align method of preparing semiconductor gates for formation of a silicide, such as a cobalt silicide (CoSi) layer, is disclosed. Deposition of silicon nitride (SiN) and low-temperature oxide (LTO) liner types, the SiN liner having an overhang structure, prevent damage to the gates while forming a self-aligned source. The undamaged gates are suitable for CoSi deposition.

Abstract translation: 公开了一种制备用于形成硅化物的半导体栅极的自对准方法，例如硅化钴（CoSi）层。 氮化硅（SiN）和低温氧化物（LTO）衬垫类型的沉积，具有突出结构的SiN衬垫防止在形成自对准源时损坏栅极。 未损坏的栅极适用于CoSi沉积。

公开(公告)号：US09449821B2

公开(公告)日：2016-09-20

申请号：US14333802

申请日：2014-07-17

Applicant: Macronix International Co., Ltd.

Inventor： Zusing Yang ,  An Chyi Wei

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/027 ,  H01L21/02 ,  H01L21/3213 ,  H01L27/115

CPC classification number: H01L21/0276 ,  H01L21/0217 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/32137 ,  H01L27/11551 ,  H01L27/11578

Abstract: High-aspect ratio trenches in integrated circuits are fabricated of composite materials and with trench boundaries having pencil-like etching profiles. The fabrication methods reduce surface tension between trench boundaries and fluids applied during manufacture, thereby avoiding pattern bending, bowing, and collapse. The method, further, facilitates fill-in of trenches with suitable selected materials.

Abstract translation: 集成电路中的高纵横比沟槽由复合材料制成，沟槽边界具有铅笔状蚀刻轮廓。 制造方法减少了沟槽边界与制造过程中应用的流体之间的表面张力，从而避免了图案弯曲，弯曲和塌陷。 此外，该方法还有助于用合适的选定材料填充沟槽。

公开(公告)号：US09337036B2

公开(公告)日：2016-05-10

申请号：US14162737

申请日：2014-01-24

Applicant: Macronix International Co., Ltd.

Inventor： Zusing Yang ,  Hong-Ji Lee

IPC: H01L21/00 ,  H01L21/16 ,  H01L21/02 ,  H01L21/027

CPC classification number: H01L21/165 ,  H01L21/02063 ,  H01L21/02068 ,  H01L21/02568 ,  H01L21/02614 ,  H01L21/02639 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/321 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76849

Abstract: Effects of copper oxide formation in semiconductor manufacture are mitigated by etching with sulfide plasmas. The plasmas form protective copper sulfide films on copper surfaces and prevent copper oxide formation. When copper oxide formation does occur, the sulfide plasmas are able to transform the copper oxide into acceptable or more conductive copper compounds. Non-oxide copper compounds are removed using clear wet strips.

Abstract translation: 半导体制造中氧化铜形成的影响通过用硫化物等离子体蚀刻来缓解。 等离子体在铜表面形成保护性硫化铜膜，防止形成铜氧化物。 当发生铜氧化物形成时，硫化物等离子体能够将氧化铜转化为可接受或更导电的铜化合物。 使用清晰的湿条除去非氧化物铜化合物。

公开(公告)号：US09287285B2

公开(公告)日：2016-03-15

申请号：US14672777

申请日：2015-03-30

Applicant: Macronix International Co., Ltd.

Inventor： Fang-Hao Hsu ,  Zusing Yang ,  Hong-Ji Lee

IPC: H01L29/78 ,  H01L27/115 ,  H01L29/40 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/423 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L27/11568 ,  H01L21/28273 ,  H01L21/823835 ,  H01L27/11521 ,  H01L29/0684 ,  H01L29/401 ,  H01L29/42324 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/518 ,  H01L29/78

Abstract: A self-align method of preparing semiconductor gates for formation of a silicide, such as a cobalt silicide (CoSi) layer, is disclosed. Deposition of silicon nitride (SiN) and low-temperature oxide (LTO) liner types, the SiN liner having an overhang structure, prevent damage to the gates while forming a self-aligned source. The undamaged gates are suitable for CoSi deposition.

公开(公告)号：US20160020211A1

公开(公告)日：2016-01-21

申请号：US14333802

申请日：2014-07-17

Applicant: Macronix International Co., Ltd.

Inventor： Zusing Yang ,  An Chyi Wei

IPC: H01L27/105 ,  H01L23/532 ,  H01L21/027 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  H01L21/02

CPC classification number: H01L21/0276 ,  H01L21/0217 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/32137 ,  H01L27/11551 ,  H01L27/11578

Abstract: High-aspect ratio trenches in integrated circuits are fabricated of composite materials and with trench boundaries having pencil-like etching profiles. The fabrication methods reduce surface tension between trench boundaries and fluids applied during manufacture, thereby avoiding pattern bending, bowing, and collapse. The method, further, facilitates fill-in of trenches with suitable selected materials.

Abstract translation: 集成电路中的高纵横比沟槽由复合材料制成，沟槽边界具有铅笔状蚀刻轮廓。 制造方法减少了沟槽边界与制造过程中应用的流体之间的表面张力，从而避免了图案弯曲，弯曲和塌陷。 此外，该方法还有助于用合适的选定材料填充沟槽。

公开(公告)号：US20150228661A1

公开(公告)日：2015-08-13

申请号：US14672777

申请日：2015-03-30

Applicant: Macronix International Co., Ltd.

Inventor： Fang-Hao Hsu ,  Zusing Yang ,  Hong-Ji Lee

IPC: H01L27/115 ,  H01L29/51 ,  H01L29/49 ,  H01L29/06

CPC classification number: H01L27/11568 ,  H01L21/28273 ,  H01L21/823835 ,  H01L27/11521 ,  H01L29/0684 ,  H01L29/401 ,  H01L29/42324 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/518 ,  H01L29/78

Abstract: A self-align method of preparing semiconductor gates for formation of a silicide, such as a cobalt silicide (CoSi) layer, is disclosed. Deposition of silicon nitride (SiN) and low-temperature oxide (LTO) liner types, the SiN liner having an overhang structure, prevent damage to the gates while forming a self-aligned source. The undamaged gates are suitable for CoSi deposition.

Abstract translation: 公开了一种制备用于形成硅化物的半导体栅极的自对准方法，例如硅化钴（CoSi）层。 氮化硅（SiN）和低温氧化物（LTO）衬垫类型的沉积，具有突出结构的SiN衬垫防止在形成自对准源时损坏栅极。 未损坏的栅极适用于CoSi沉积。