Some embodiments of the present disclosure relate to a split gate memory cell which includes a select gate and a memory gate. The select gate has a planar upper surface disposed over a semiconductor substrate and is separated from the substrate by a gate dielectric layer. The memory gate has a planar upper surface arranged at one side of the select gate and is separated from the substrate by a charge trapping layer. The charge trapping layer extends under the memory gate. A first spacer is disposed above the memory gate and is separated from the memory gate by a first dielectric liner. The first dielectric liner extends upwardly along an upper sidewall of the charge trapping layer; and source/drain regions are disposed in the semiconductor substrate at opposite sides of the select gate and the memory gate.