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公开(公告)号：US20160043097A1
公开(公告)日：2016-02-11
申请号：US14454872
申请日：2014-08-08
发明人： Wei-Hang Huang , Chang-Ming Wu , Shih-Chang Liu
IPC分类号： H01L27/115 , H01L29/66 , H01L21/02 , H01L29/51 , H01L21/28 , H01L29/45 , H01L29/792 , H01L29/423
CPC分类号： H01L27/11568 , H01L21/0217 , H01L21/28282 , H01L29/42344 , H01L29/456 , H01L29/513 , H01L29/518 , H01L29/665 , H01L29/6656 , H01L29/66833 , H01L29/792
摘要： The present disclosure relates to a self-aligned split gate memory cell, and an associated method. The self-aligned split gate memory cell has memory gate and select gate covered upper surfaces by some spacers. Thus the memory gate and select gate are protected from silicide. The memory gate and select gate are defined self-aligned by the said spacers. The memory gate and select gate are formed by etching back corresponding conductive materials not covered by the spacers instead of recess processes. Thus the memory gate and select gate have flat upper surfaces and are well defined. The disclosed device and method is also capable of further scaling since photolithography processes are reduced.
摘要翻译： 本公开涉及自对准分离门存储器单元及其相关方法。 自对准分离栅极存储单元具有存储栅极和通过一些间隔物选择栅极覆盖的上表面。 因此，存储器栅极和选择栅极被保护以防止硅化物。 存储器栅极和选择栅极被所述间隔物自对准地限定。 存储栅极和选择栅极通过蚀刻不被间隔物覆盖的相应导电材料而不是凹陷工艺而形成。 因此，存储器栅极和选择栅极具有平坦的上表面并且被明确定义。 所公开的装置和方法还能够进一步缩放，因为光刻工艺被减少。
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公开(公告)号：US20210043832A1
公开(公告)日：2021-02-11
申请号：US17065606
申请日：2020-10-08
摘要： An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.
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公开(公告)号：US10825825B2
公开(公告)日：2020-11-03
申请号：US16510043
申请日：2019-07-12
IPC分类号： H01L27/11568 , H01L29/78 , H01L21/28 , H01L29/34 , H01L29/423 , H01L29/66 , H01L29/788 , H01L27/11521 , H01L23/528 , H01L29/49 , H01L21/768
摘要： Semiconductor structures are provided. The semiconductor structure includes a substrate and a first gate electrode formed over the substrate. The semiconductor structure further includes a dielectric layer formed on a sidewall of the first gate electrode and a second gate electrode formed over the substrate and separated from the first gate electrode by the dielectric layer. The semiconductor structure further includes a contact formed over the second gate electrode. In addition, the contact has a first extending portion and a second extending portion extending along opposite sidewalls of the second gate electrode.
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公开(公告)号：US10529916B2
公开(公告)日：2020-01-07
申请号：US15463500
申请日：2017-03-20
摘要： An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.
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5.发明授权Self-aligned split gate flash memory having liner-separated spacers above the memory gate 有权自对准分离栅极闪存，其在存储器栅极上方具有衬垫分离的间隔物公开(公告)号：US09391085B2
公开(公告)日：2016-07-12
申请号：US14454872
申请日：2014-08-08
发明人： Wei-Hang Huang , Chang-Ming Wu , Shih-Chang Liu
IPC分类号： H01L29/66 , H01L27/115 , H01L29/792 , H01L29/423 , H01L29/51 , H01L21/28 , H01L29/45 , H01L21/02
CPC分类号： H01L27/11568 , H01L21/0217 , H01L21/28282 , H01L29/42344 , H01L29/456 , H01L29/513 , H01L29/518 , H01L29/665 , H01L29/6656 , H01L29/66833 , H01L29/792
摘要： Some embodiments of the present disclosure relate to a split gate memory cell which includes a select gate and a memory gate. The select gate has a planar upper surface disposed over a semiconductor substrate and is separated from the substrate by a gate dielectric layer. The memory gate has a planar upper surface arranged at one side of the select gate and is separated from the substrate by a charge trapping layer. The charge trapping layer extends under the memory gate. A first spacer is disposed above the memory gate and is separated from the memory gate by a first dielectric liner. The first dielectric liner extends upwardly along an upper sidewall of the charge trapping layer; and source/drain regions are disposed in the semiconductor substrate at opposite sides of the select gate and the memory gate.
摘要翻译： 本公开的一些实施例涉及包括选择栅极和存储器栅极的分离栅极存储器单元。 选择栅极具有设置在半导体衬底上的平面上表面，并且通过栅极介电层与衬底分离。 存储器栅极具有布置在选择栅极的一侧的平面上表面，并且通过电荷捕获层与衬底分离。 电荷捕获层在存储栅下方延伸。 第一间隔件设置在存储器栅极上方并且通过第一电介质衬垫与存储器栅极分离。 第一电介质衬垫沿电荷俘获层的上侧壁向上延伸; 并且源极/漏极区域在选择栅极和存储栅极的相对侧设置在半导体衬底中。
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公开(公告)号：US11258007B2
公开(公告)日：2022-02-22
申请号：US17065606
申请日：2020-10-08
摘要： An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.
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公开(公告)号：US20160043306A1
公开(公告)日：2016-02-11
申请号：US14918671
申请日：2015-10-21
摘要： An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.
摘要翻译： 集成电路器件包括衬底和磁隧道结（MTJ）。 MTJ至少包括钉扎层，阻挡层和自由层。 MTJ形成在衬底的表面上。 在被钉扎层，阻挡层和自由层中，自由层首先形成并且最接近表面。 这使得在蚀刻自由层之前，可以在自由层的周边区域上形成间隔物。 由蚀刻或其它自由层边界限定工艺导致的对自由层的任何损伤通过间隔物保持与隧道结一定距离。
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公开(公告)号：US09048316B2
公开(公告)日：2015-06-02
申请号：US14013653
申请日：2013-08-29
IPC分类号： H01L27/115 , G11C16/16 , H01L29/78 , H01L21/28
CPC分类号： H01L27/11568 , H01L21/28 , H01L21/28273 , H01L21/28282 , H01L21/76805 , H01L23/528 , H01L27/11521 , H01L29/34 , H01L29/42324 , H01L29/4234 , H01L29/4916 , H01L29/66825 , H01L29/7831 , H01L29/788 , H01L29/7881 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of mechanisms of a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a word line cell disposed over the substrate. The semiconductor device further includes a memory gate disposed over the substrate and adjacent to the word line cell and a spacer on a sidewall of the memory gate. The spacer and the word line cell are at opposite sides of the memory gate. In addition, an angle between a top surface of the memory gate and a sidewall of the memory gate is in a range from about 75° to about 90°.
摘要翻译： 提供半导体器件结构的机构的实施例。 半导体器件结构包括衬底和设置在衬底上的字线单元。 半导体器件还包括设置在衬底上并与字线单元相邻并且在存储器栅极的侧壁上的间隔物的存储器栅极。 间隔物和字线单元位于存储器栅极的相对侧。 此外，存储器栅极的顶表面和存储器栅极的侧壁之间的角度在约75°至约90°的范围内。
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公开(公告)号：US10355011B2
公开(公告)日：2019-07-16
申请号：US15855940
申请日：2017-12-27
IPC分类号： H01L21/28 , H01L29/34 , H01L29/49 , H01L29/66 , H01L29/78 , H01L21/768 , H01L23/528 , H01L29/423 , H01L29/788 , H01L27/11521 , H01L27/11568
摘要： Methods for forming semiconductor structures are provided. The method for forming the semiconductor structure includes forming a control gate over a substrate and forming a dielectric layer covering the control gate. The method further includes forming a conductive layer having a first portion and a second portion over the dielectric layer. In addition, the first portion of the conductive layer is separated from the control gate by the dielectric layer. The method further includes forming an oxide layer on a top surface of the first portion of the conductive layer and removing the second portion of the conductive layer to form a memory gate.
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公开(公告)号：US09859295B2
公开(公告)日：2018-01-02
申请号：US15425647
申请日：2017-02-06
IPC分类号： H01L27/11568 , H01L29/49 , H01L29/423 , H01L21/28 , H01L21/768
CPC分类号： H01L27/11568 , H01L21/28 , H01L21/28273 , H01L21/28282 , H01L21/76805 , H01L23/528 , H01L27/11521 , H01L29/34 , H01L29/42324 , H01L29/4234 , H01L29/4916 , H01L29/66825 , H01L29/7831 , H01L29/788 , H01L29/7881 , H01L2924/0002 , H01L2924/00
摘要： Methods for forming semiconductor structures are provided. The method for forming the semiconductor structure includes forming a word line cell over a substrate and forming a dielectric layer over the word line cell. The method further includes forming a conductive layer over the dielectric layer and polishing the conductive layer until the dielectric layer is exposed. The method further includes forming an oxide layer on a top surface of the conductive layer and removing portions of the conductive layer not covered by the oxide layer to form a memory gate.
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