Invention Grant
- Patent Title: Fractional-N synthesizer with pre-multiplication
- Patent Title (中): 具有预乘法的分数N合成器
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Application No.: US14709759Application Date: 2015-05-12
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Publication No.: US09509323B2Publication Date: 2016-11-29
- Inventor: Krishnaswamy Thiagarajan , Jagdish Chand Goyal , Srikanth Manian , Debapriya Sahu
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Michael A. Davis, Jr.; Frank D. Cimino
- Main IPC: H03D3/24
- IPC: H03D3/24 ; H03L7/197 ; H04B1/40 ; H04L7/033 ; H03L7/081

Abstract:
A fractional-N frequency synthesizer that suppresses integer boundary spurs. A frequency synthesizer includes a fractional-N phase locked loop (PLL) and a reference frequency scaler. The reference frequency scaler is coupled to a reference clock input of the PLL, the reference frequency scaler includes a programmable frequency divider, and a programmable frequency multiplier connected in series with the programmable frequency divider. Each of the divider and multiplier is configured to scale a reference frequency provided to the PLL by a programmable integer value.
Public/Granted literature
- US20150326236A1 FRACTIONAL-N SYNTHESIZER WITH PRE-MULTIPLICATION Public/Granted day:2015-11-12
Information query
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