Invention Grant
US09509323B2 Fractional-N synthesizer with pre-multiplication 有权
具有预乘法的分数N合成器

Fractional-N synthesizer with pre-multiplication
Abstract:
A fractional-N frequency synthesizer that suppresses integer boundary spurs. A frequency synthesizer includes a fractional-N phase locked loop (PLL) and a reference frequency scaler. The reference frequency scaler is coupled to a reference clock input of the PLL, the reference frequency scaler includes a programmable frequency divider, and a programmable frequency multiplier connected in series with the programmable frequency divider. Each of the divider and multiplier is configured to scale a reference frequency provided to the PLL by a programmable integer value.
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