公开(公告)号：US20160126895A1

公开(公告)日：2016-05-05

申请号：US14529056

申请日：2014-10-30

Applicant: Texas Instruments Incorporated

Inventor： Gireesh Rajendran ,  Rakesh Kumar ,  Alok Prakask Joshi ,  Subhashish Mukherjee ,  Krishnaswamy Thiagarajan ,  Apu Sivadas

IPC: H03F1/02 ,  H03F3/19 ,  H04L27/34 ,  H03F3/217

CPC classification number: H04L27/3405 ,  H03F1/0227 ,  H03F3/19 ,  H03F3/217 ,  H03F3/245 ,  H03F2200/331 ,  H03F2200/336 ,  H03F2200/451

Abstract: An I converter outputs I sign data and I magnitude data based on received I data. A Q converter outputs Q sign data and Q magnitude data based on received Q data. An I clock generates an I phase based ort the I sign data. A Q clock generates a Q phase based on the Q sign data. An I modulator generates an I magnitude pulse stream based on the I magnitude data. A Q modulator generates a Q magnitude pulse stream based on the Q magnitude data. A digital logic component generates an output signal based on the I phase, the I magnitude pulse stream, the Q phase and the Q magnitude pulse stream. A power amplifier generates an amplified signal based on the output signal.

Abstract translation: I转换器根据接收到的I数据输出I符号数据和I幅度数据。 Q转换器基于接收的Q数据输出Q符号数据和Q幅度数据。 一个I时钟产生一个I相或ort的I符号数据。 Q时钟基于Q符号数据生成Q相。 I调制器基于I幅度数据生成I幅度脉冲流。 Q调制器基于Q幅度数据产生Q幅度脉冲流。 数字逻辑部件基于I相，I幅度脉冲流，Q相和Q幅度脉冲流产生输出信号。 功率放大器基于输出信号产生放大信号。

公开(公告)号：US09948312B2

公开(公告)日：2018-04-17

申请号：US15443217

申请日：2017-02-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jayawardan Janardhanan ,  Krishnaswamy Thiagarajan ,  Jagdish Chand Goyal

IPC: H03L7/087 ,  H03L7/06 ,  H03L7/00 ,  H03L7/08 ,  H03L7/089

CPC classification number: H03L7/087 ,  H03L7/0895 ,  H03L7/1072 ,  H03L7/113

Abstract: A phase lock loop (PLL) includes a voltage-controlled oscillator (VCO) and a frequency detector to generate a FAST signal responsive to a frequency of a reference signal being greater than the frequency of a feedback signal derived from the VCO and to generate a SLOW signal responsive to the frequency of the reference signal being smaller than the frequency of the feedback signal. The PLL also includes a digital charge pump, a loop filter, and a state machine circuit. Responsive to receipt of multiple consecutive FAST signals when the digital charge pump is providing a charging current to the loop filter, the state machine circuit reconfigures the digital charge pump to increase the charging current to the loop filter. Responsive to receipt of multiple consecutive SLOW signals when the loop filter is discharging, the state machine circuit reconfigures the digital charge pump to cause the loop filter's discharge current to increase. Upon detection of a terminal condition, the state machine circuit may disable the digital charge pump and enable operation of an analog charge pump.

公开(公告)号：US09667300B2

公开(公告)日：2017-05-30

申请号：US14753940

申请日：2015-06-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jagdish Chand Goyal ,  Krishnaswamy Thiagarajan ,  Jayawardan Janardhanan ,  Srikanth Manian

IPC: H04B1/40 ,  H03L7/107 ,  H03L7/197

CPC classification number: H04B1/40 ,  H03L7/1075 ,  H03L7/1976

Abstract: A frequency synthesizer that includes a reference frequency scaler and a phase locked loop (PLL) coupled to the reference frequency scaler. The reference frequency scaler is configured to generate a first reference frequency and a second reference frequency. The PLL is configured to generate a first output frequency based on the first reference frequency during a first timeslot and a second output frequency based on the second reference frequency during a second timeslot. The PLL comprises a loop filter that includes a first switch connected in series to a first capacitor and configured to close during the first timeslot and a second switch connected in series to a second capacitor and configured to open during the first timeslot.

公开(公告)号：US20150214907A1

公开(公告)日：2015-07-30

申请号：US14165251

申请日：2014-01-27

Applicant: Texas Instruments Incorporated

Inventor： APU SIVADAS ,  Alok Joshi ,  Krishnaswamy Thiagarajan ,  Rakesh Kumar

IPC: H03F3/21 ,  H03F3/213 ,  H03F3/24

CPC classification number: H03F3/211 ,  H03F3/195 ,  H03F3/245 ,  H03F3/72 ,  H03F2200/537 ,  H03F2200/541 ,  H03F2203/21145 ,  H03F2203/7221 ,  H03F2203/7236

Abstract: According to an aspect of present disclosure, a set of power amplifiers are used to amplify power of a signal for transmission. The signal powers from a set of power amplifiers are coupled to set of primary windings which are commonly coupled to a secondary winding such that the powers on the primary windings are additive in the secondary winding. A current path on the primary side is provided for flow of a current that is induced on at least one primary winding when a power amplifier coupled to that primary winding is in “off” state. As a result, the induced current is prevented from flowing in to the power amplifier that are in “on” state. Further, the current path isolates the power amplifiers from each other thereby enabling the power amplifiers to operate at the rated efficiency. In one embodiment, the current path is provided using a resistor network.

Abstract translation: 根据本公开的一个方面，使用一组功率放大器来放大用于传输的信号的功率。 来自一组功率放大器的信号功率耦合到通常耦合到次级绕组的初级绕组组，使得初级绕组上的功率在次级绕组中是相加的。 当耦合到该初级绕组的功率放大器处于“关闭”状态时，提供初级侧上的电流路径用于在至少一个初级绕组上感应的电流的流动。 结果，防止感应电流流入处于“接通”状态的功率放大器。 此外，电流路径将功率放大器彼此隔离，从而使得功率放大器能够以额定效率工作。 在一个实施例中，使用电阻网络提供电流路径。

公开(公告)号：US09509323B2

公开(公告)日：2016-11-29

申请号：US14709759

申请日：2015-05-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Krishnaswamy Thiagarajan ,  Jagdish Chand Goyal ,  Srikanth Manian ,  Debapriya Sahu

IPC: H03D3/24 ,  H03L7/197 ,  H04B1/40 ,  H04L7/033 ,  H03L7/081

CPC classification number: H03L7/1976 ,  H03L7/0814 ,  H03L7/1974 ,  H03L2207/10 ,  H04B1/40 ,  H04L7/033 ,  H04L7/0331

Abstract: A fractional-N frequency synthesizer that suppresses integer boundary spurs. A frequency synthesizer includes a fractional-N phase locked loop (PLL) and a reference frequency scaler. The reference frequency scaler is coupled to a reference clock input of the PLL, the reference frequency scaler includes a programmable frequency divider, and a programmable frequency multiplier connected in series with the programmable frequency divider. Each of the divider and multiplier is configured to scale a reference frequency provided to the PLL by a programmable integer value.

Abstract translation: 一个抑制整数边界杂散的分数N频率合成器。 频率合成器包括分数N锁相环（PLL）和参考频率缩放器。 参考频率缩放器耦合到PLL的参考时钟输入，参考频率缩放器包括可编程分频器和与可编程分频器串联连接的可编程倍频器。 分频器和乘法器中的每一个被配置为通过可编程整数值来缩放提供给PLL的参考频率。

公开(公告)号：US09450546B2

公开(公告)日：2016-09-20

申请号：US14165251

申请日：2014-01-27

Applicant: Texas Instruments Incorporated

Inventor： Apu Sivadas ,  Alok Joshi ,  Krishnaswamy Thiagarajan ,  Rakesh Kumar

IPC: H03F3/21 ,  H03F3/213 ,  H03F3/24 ,  H03F3/195 ,  H03F3/72

CPC classification number: H03F3/211 ,  H03F3/195 ,  H03F3/245 ,  H03F3/72 ,  H03F2200/537 ,  H03F2200/541 ,  H03F2203/21145 ,  H03F2203/7221 ,  H03F2203/7236

Abstract: According to an aspect of present disclosure, a set of power amplifiers are used to amplify power of a signal for transmission. The signal powers from a set of power amplifiers are coupled to set of primary windings which are commonly coupled to a secondary winding such that the powers on the primary windings are additive in the secondary winding. A current path on the primary side is provided for flow of a current that is induced on at least one primary winding when a power amplifier coupled to that primary winding is in “off” state. As a result, the induced current is prevented from flowing in to the power amplifier that are in “on” state. Further, the current path isolates the power amplifiers from each other thereby enabling the power amplifiers to operate at the rated efficiency. In one embodiment, the current path is provided using a resistor network.

Abstract translation: 根据本公开的一个方面，使用一组功率放大器来放大用于传输的信号的功率。 来自一组功率放大器的信号功率耦合到通常耦合到次级绕组的初级绕组组，使得初级绕组上的功率在次级绕组中是相加的。 当耦合到该初级绕组的功率放大器处于“关闭”状态时，提供初级侧上的电流路径用于在至少一个初级绕组上感应的电流的流动。 结果，防止感应电流流入处于“接通”状态的功率放大器。 此外，电流路径将功率放大器彼此隔离，从而使得功率放大器能够以额定效率工作。 在一个实施例中，使用电阻网络提供电流路径。