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公开(公告)号：US10924309B2
公开(公告)日：2021-02-16
申请号：US16793486
申请日：2020-02-18
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Yogesh Darwhekar , Pranav Kumar , Arpan Thakkar , Naveen Mahadev , Srikanth Manian
IPC: H04L27/00 , H04L27/38 , H04L27/152 , H04L27/148
Abstract: A receiver circuit includes a quadrature signal generator to generate an in-phase (I) signal and a quadrature (Q) signal from a local oscillator signal and an IQ phase sense and control circuit to generate a phase adjustment code responsive to a phase error between quadrature signals generated by a plurality of mixers. The receiver circuit also includes a phase corrector to adjust a phase difference between the I and Q signals from the quadrature signal generator to generate corrected I and Q signals to be provided to the plurality of mixers.
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公开(公告)号：US10243573B1
公开(公告)日：2019-03-26
申请号：US15959332
申请日：2018-04-23
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Jagdish Chand Goyal , Peeyoosh Mirajkar , Shankaranarayana Karantha , Ashwin Ravisankar , Srikanth Manian , Srinivas Theertham
Abstract: Frequency synthesis is based on phase synchronizing PLL output across REFERENCE and VCO clock domains (including outputs for multiple PLLs), based on an input (REF-Domain) SYNC signal (phase timing reference). A frequency synthesizer includes a VCO to generate VCO_clk and a PLL output circuit, such as a channel divider, to generate PLL_OUT based on VCO_clk (in the VCO-Domain). The VCO loop includes a PD to phase compare an input PD_clock based on REF_CLK, and a VCO feedback signal based on divided VCO_clk (NDIV_out). SYNC alignment circuitry generates a SYNC alignment signal based on SYNC, PD_clk, and NDIV_out (REF-Domain), which is used to synchronize the PLL output circuit and PLL_OUT to SYNC. If a reference divider generates PD_clk, the SYNC alignment circuitry generates a reset to SYNC-align the reference divider. If the VCO loop uses fractional divide, the SYNC alignment circuitry resets the fractional modulator to a known sequence.
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公开(公告)号：US20240136977A1
公开(公告)日：2024-04-25
申请号：US17972532
申请日：2022-10-23
Applicant: Texas Instruments Incorporated
Inventor： Srikanth Manian , Sumantra Seth , Trilok Kamagond
CPC classification number: H03F1/02 , H03F3/45475 , H03F2200/129
Abstract: A driver includes an operational amplifier which includes a first amplifier input coupled to a first driver input, a second amplifier input coupled to a second driver input, a first amplifier output, a second amplifier output, a third amplifier output and a fourth amplifier output. The first amplifier output is coupled to the first driver output and the third amplifier output is coupled to the second driver output in a voltage-mode operation. The second amplifier output is coupled to the first driver output and the fourth amplifier output is coupled to the second driver output in a current-mode operation.
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公开(公告)号：US11509266B2
公开(公告)日：2022-11-22
申请号：US17493922
申请日：2021-10-05
Applicant: Texas Instruments Incorporated
Inventor： Srinivas Theertham , Srikanth Manian , Uday Kiran Meda
Abstract: A system includes a data path and a phase-locked loop (PLL) coupled to the data path. The system also includes a voltage-controlled oscillator (VCO) coupled to the PLL. The VCO includes an LC circuit with first and second differential output terminals. The VCO also includes a first resistor coupled between the first differential output terminal and drain terminals of a first pair of complementary metal-oxide semiconductor (CMOS) transistors. The VCO also includes a second resistor coupled between the second differential output terminal and drain terminals of a second pair of CMOS transistors.
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公开(公告)号：US09762292B2
公开(公告)日：2017-09-12
申请号：US14040275
申请日：2013-09-27
Applicant: Texas Instruments Incorporated
Inventor： Srikanth Manian , Yogesh Darwhekar , Abhishek Agrawal , Koby Levy , Yaniv Tzoreff , Erez Shalom
IPC: H04B5/00
CPC classification number: H04B5/0037
Abstract: A method of charging a power harvested supply in an electronic communication device, which can be an NFC (near field communication) device. The power harvested supply in the electronic communication device is charged without causing dV/V violation and avoids false wake up. An RF (radio frequency) field is received at the antenna of the electronic communication device. A differential voltage is generated from the RF field at a first tag pin and a second tag pin of the electronic communication device. A bandgap reference voltage and a reference current are generated in response to the differential voltage. A shunt current is generated in response to the differential voltage and the bandgap reference voltage. A bank of switching devices is activated if the shunt current is more than the reference current.
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Patent Agency Ranking
公开(公告)号：US20210119619A1
公开(公告)日：2021-04-22
申请号：US16905264
申请日：2020-06-18
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Srijan Rastogi , Srikanth Manian
Abstract: A serial bus re-driver circuit includes an edge detector circuit and a booster circuit. The edge detector circuit is configured to detect a transition of serial bus signal. The booster circuit is coupled to the edge detector circuit, and is configured to switch current to the serial bus signal. The booster circuit includes a leading edge boost pulse generation circuit and a trailing edge boost pulse generation circuit. The leading edge boost pulse generation circuit is configured to switch a first current pulse to the serial bus signal at the transition of the serial bus signal. The trailing edge boost pulse generation circuit is configured to switch a second current pulse to the serial bus signal. The second current pulse is shorter than the first current pulse.
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公开(公告)号：US10608853B1
公开(公告)日：2020-03-31
申请号：US16130087
申请日：2018-09-13
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Yogesh Darwhekar , Pranav Kumar , Arpan Thakkar , Naveen Mahadev , Srikanth Manian
IPC: H04L27/00 , H04L27/38 , H04L27/152 , H04L27/148
Abstract: A receiver circuit includes a quadrature signal generator to generate an in-phase (I) signal and a quadrature (Q) signal from a local oscillator signal and an IQ phase sense and control circuit to generate a phase adjustment code responsive to a phase error between quadrature signals generated by a plurality of mixers. The receiver circuit also includes a phase corrector to adjust a phase difference between the I and Q signals from the quadrature signal generator to generate corrected I and Q signals to be provided to the plurality of mixers.
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公开(公告)号：US20170187515A1
公开(公告)日：2017-06-29
申请号：US15388407
申请日：2016-12-22
Applicant: Texas Instruments Incorporated
Inventor： Yogesh Darwhekar , Srikanth Manian , Srinivas Theertham , Jagdish Chand Goyal , Robert Karl Butler
CPC classification number: H04L27/261 , H03L7/099 , H03L7/1976
Abstract: The disclosure provides a frequency synthesizer. It includes a PFD that generates an up signal and a down signal in response to a reference signal and a feedback signal. A charge pump generates a control voltage in response to the up signal and the down signal. A low pass filter generates a filtered voltage in response to the control voltage. An oscillator circuit generates an output signal in response to the filtered voltage. A feedback divider is coupled between the oscillator circuit and the PFD, and divides the output signal by a first integer divider to generate the feedback signal. A sigma delta modulator (SDM) generates a second integer divider in response to the feedback signal, the reference signal, the output signal and the first integer divider. A digital filter is coupled between the SDM and the feedback divider, and filters quantization noise associated with the SDM.
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公开(公告)号：US20240235480A9
公开(公告)日：2024-07-11
申请号：US17972532
申请日：2022-10-24
Applicant: Texas Instruments Incorporated
Inventor： Srikanth Manian , Sumantra Seth , Trilok Kamagond
CPC classification number: H03F1/02 , H03F3/45475 , H03F2200/129
Abstract: A driver includes an operational amplifier which includes a first amplifier input coupled to a first driver input, a second amplifier input coupled to a second driver input, a first amplifier output, a second amplifier output, a third amplifier output and a fourth amplifier output. The first amplifier output is coupled to the first driver output and the third amplifier output is coupled to the second driver output in a voltage-mode operation. The second amplifier output is coupled to the first driver output and the fourth amplifier output is coupled to the second driver output in a current-mode operation.
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公开(公告)号：US11711072B2
公开(公告)日：2023-07-25
申请号：US16905264
申请日：2020-06-18
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Srijan Rastogi , Srikanth Manian
CPC classification number: H03K5/01 , H03K3/037 , H03K19/20 , H03K2005/00019
Abstract: A serial bus re-driver circuit includes an edge detector circuit and a booster circuit. The edge detector circuit is configured to detect a transition of serial bus signal. The booster circuit is coupled to the edge detector circuit, and is configured to switch current to the serial bus signal. The booster circuit includes a leading edge boost pulse generation circuit and a trailing edge boost pulse generation circuit. The leading edge boost pulse generation circuit is configured to switch a first current pulse to the serial bus signal at the transition of the serial bus signal. The trailing edge boost pulse generation circuit is configured to switch a second current pulse to the serial bus signal. The second current pulse is shorter than the first current pulse.
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