发明授权
US09530844B2 Transistor structures having reduced electrical field at the gate oxide and methods for making same
有权
在栅极氧化物处具有减小的电场的晶体管结构及其制造方法
- 专利标题： Transistor structures having reduced electrical field at the gate oxide and methods for making same
- 专利标题（中）： 在栅极氧化物处具有减小的电场的晶体管结构及其制造方法
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申请号： US13730133申请日： 2012-12-28
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公开(公告)号： US09530844B2公开(公告)日： 2016-12-27
- 发明人: Qingchun Zhang , Brett Hull
- 申请人： Cree, Inc.
- 申请人地址： US NC Durham
- 专利权人： Cree, Inc.
- 当前专利权人： Cree, Inc.
- 当前专利权人地址： US NC Durham
- 代理商 Anthony J. Josephson
- 主分类号： H01L29/732
- IPC分类号： H01L29/732 ; H01L29/66 ; H01L29/16 ; H01L29/739 ; H01L29/749 ; H01L29/78 ; H01L29/06 ; H01L29/08
摘要：
A transistor device having reduced electrical field at the gate oxide interface is disclosed. In one embodiment, the transistor device comprises a gate, a source, and a drain, wherein the gate is at least partially in contact with a gate oxide. The transistor device has a P+ region within a JFET region of the transistor device in order to reduce an electrical field on the gate oxide.
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