公开(公告)号：US20220262909A1

公开(公告)日：2022-08-18

申请号：US17177641

申请日：2021-02-17

申请人： Cree, Inc.

发明人： Daniel Jenner Lichtenwalner ,  Edward Robert Van Brunt ,  Thomas E. Harrington, III ,  Shadi Sabri ,  Brett Hull ,  Brice McPherson ,  Joe W. McPherson

IPC分类号： H01L29/40

摘要： Strategic placement and patterning of electrodes, vias, and metal runners can significantly reduce strain in a power semiconductor die. By modifying the path defining electrodes, vias, and metal runners, as well as patterning the material layers thereof, strain can be better managed to increase reliability of a power semiconductor die.

公开(公告)号：US20220140132A1

公开(公告)日：2022-05-05

申请号：US17088686

申请日：2020-11-04

申请人： Cree, Inc.

发明人： Edward Robert Van Brunt ,  Joe W. McPherson ,  Thomas E. Harrington, III ,  Sei-Hyung Ryu ,  Brett Hull ,  In-Hwan Ji

IPC分类号： H01L29/78 ,  H01L29/16 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L23/31

摘要： Semiconductor devices, and more particularly passivation structures for semiconductor devices are disclosed. A semiconductor device may include an active region, an edge termination region that is arranged along a perimeter of the active region, and a passivation structure that may form a die seal along the edge termination region. The passivation structure may include a number of passivation layers in an arrangement that improves mechanical strength and adhesion of the passivation structure along the edge termination region. An interface formed by at least one of the passivation layers may be provided with a pattern that serves to more evenly distribute forces related to thermal expansion and contraction during power cycling, thereby reducing cracking and delamination in the passivation structure. A patterned layer may be at least partially embedded in the passivation structure in an arrangement that forms the corresponding pattern in overlying portions of the passivation structure.

公开(公告)号：US11184001B2

公开(公告)日：2021-11-23

申请号：US16811526

申请日：2020-03-06

申请人： Cree, Inc.

发明人： Qingchun Zhang ,  Adam Barkley ,  Sei-Hyung Ryu ,  Brett Hull

IPC分类号： H01L29/78 ,  H03K17/12 ,  H01L29/423 ,  H01L29/10 ,  H01L29/739 ,  H01L29/06 ,  H01L29/16 ,  H01L29/417 ,  H01L29/40

摘要： Power switching devices include a semiconductor layer structure that has an active region and an inactive region. The active region includes a plurality of unit cells and the inactive region includes a field insulating layer on the semiconductor layer structure and a gate bond pad on the field insulating layer opposite the semiconductor layer structure. A gate insulating pattern is provided on the semiconductor layer structure between the active region and the field insulating layer, and at least one source/drain contact is provided on the semiconductor layer structure between the gate insulating pattern and the field insulating layer.

公开(公告)号：US20190013416A1

公开(公告)日：2019-01-10

申请号：US15642634

申请日：2017-07-06

申请人： Cree, Inc.

发明人： Qingchun Zhang ,  Edward R. Van Brunt ,  Brett Hull ,  Scott Thomas Allen

IPC分类号： H01L29/872 ,  H01L29/66 ,  H01L29/06

摘要： A Schottky diode includes a drift region, a channel in an upper portion of the drift region, and first and second adjacent blocking junctions in the upper portion of the drift region that define the channel therebetween. The drift region and channel are doped with dopants having a first conductivity type, and the first and second blocking junctions doped with dopants having a second conductivity type that is opposite the first conductivity type. The blocking junctions extend at least one micron into the upper portion of the drift region and are spaced apart from each other by less than 3.0 microns.

公开(公告)号：US20200212908A1

公开(公告)日：2020-07-02

申请号：US16811526

申请日：2020-03-06

申请人： Cree, Inc.

发明人： Qingchun Zhang ,  Adam Barkley ,  Sei-Hyung Ryu ,  Brett Hull

IPC分类号： H03K17/12 ,  H01L29/739 ,  H01L29/417 ,  H01L29/16 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/423

摘要： Power switching devices include a semiconductor layer structure that has an active region and an inactive region. The active region includes a plurality of unit cells and the inactive region includes a field insulating layer on the semiconductor layer structure and a gate bond pad on the field insulating layer opposite the semiconductor layer structure. A gate insulating pattern is provided on the semiconductor layer structure between the active region and the field insulating layer, and at least one source/drain contact is provided on the semiconductor layer structure between the gate insulating pattern and the field insulating layer.

公开(公告)号：US20170053987A1

公开(公告)日：2017-02-23

申请号：US15344735

申请日：2016-11-07

申请人： Cree, Inc.

发明人： Qingchun Zhang ,  Brett Hull

IPC分类号： H01L29/16 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/739 ,  H01L29/749 ,  H01L29/06 ,  H01L29/10

CPC分类号： H01L29/7802 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66333 ,  H01L29/66378 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/749 ,  H01L29/7827 ,  H01L29/7828

摘要： A transistor device having reduced electrical field at the gate oxide interface is disclosed. In one embodiment, the transistor device comprises a gate, a source, and a drain, wherein the gate is at least partially in contact with a gate oxide. The transistor device has a P+ region within a JFET region of the transistor device in order to reduce an electrical field on the gate oxide.

摘要翻译： 公开了一种在栅极氧化物界面处具有减小的电场的晶体管器件。 在一个实施例中，晶体管器件包括栅极，源极和漏极，其中栅极至少部分地与栅极氧化物接触。 晶体管器件在晶体管器件的JFET区域内具有P +区域，以便减小栅极氧化物上的电场。

公开(公告)号：US20210336021A1

公开(公告)日：2021-10-28

申请号：US16854959

申请日：2020-04-22

申请人： Cree, Inc.

发明人： Daniel Jenner Lichtenwalner ,  Brett Hull ,  Edward Robert Van Brunt ,  Shadi Sabri ,  Matt N. McCain

IPC分类号： H01L29/423 ,  H01L29/06 ,  H01L29/739 ,  H01L29/66 ,  H01L29/40 ,  H01L29/78

摘要： A semiconductor device includes a semiconductor layer structure that includes silicon carbide, a gate dielectric layer on the semiconductor layer structure, and a gate electrode on the gate dielectric layer opposite the semiconductor layer structure. In some embodiments, a periphery of a portion of the gate dielectric layer that underlies the gate electrode is thicker than a central portion of the gate dielectric layer, and a lower surface of the gate electrode has recessed outer edges such as rounded and/or beveled outer edges.

公开(公告)号：US10861931B2

公开(公告)日：2020-12-08

申请号：US15372505

申请日：2016-12-08

申请人： Cree, Inc.

发明人： Daniel J. Lichtenwalner ,  Edward R. Van Brunt ,  Brett Hull

IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L21/04 ,  H01L29/66 ,  H01L29/739 ,  H01L29/16 ,  H01L29/08

摘要： Semiconductor devices include a semiconductor layer structure comprising a drift region that includes a wide band-gap semiconductor material. A shielding pattern is provided in an upper portion of the drift region in an active region of the device and a termination structure is provided in the upper portion of the drift region in a termination region of the device. A gate trench extends into an upper surface of the semiconductor layer structure. The semiconductor layer structure includes a semiconductor layer that extends above and at least partially covers the termination structure.

公开(公告)号：US20200295174A1

公开(公告)日：2020-09-17

申请号：US16353313

申请日：2019-03-14

申请人： Cree, Inc.

发明人： Shadi Sabri ,  Daniel Lichtenwalner ,  Edward Robert Van Brunt ,  Scott Thomas Allen ,  Brett Hull

IPC分类号： H01L29/78 ,  H01L29/16 ,  H01L29/08 ,  H01L29/66 ,  H01L29/739 ,  H01L29/423

摘要： Semiconductor devices include a plurality of gate fingers extending on a wide bandgap semiconductor layer structure. An inter-metal dielectric pattern is formed on the gate fingers, the inter-metal dielectric pattern including a plurality of dielectric fingers that cover the respective gate fingers. A top-side metallization is provided on the inter-metal dielectric pattern and on exposed portions of the upper surface of the wide bandgap semiconductor layer structure. The top-side metallization includes a first conductive diffusion barrier layer on the inter-metal dielectric pattern and on the exposed portions of the upper surface of the wide bandgap semiconductor layer structure, a conductive contact layer on an upper surface of the first conductive diffusion barrier layer, and a grain stop layer buried within the conductive contact layer.

公开(公告)号：US10601413B2

公开(公告)日：2020-03-24

申请号：US15699149

申请日：2017-09-08

申请人： Cree, Inc.

发明人： Qingchun Zhang ,  Adam Barkley ,  Sei-Hyung Ryu ,  Brett Hull

IPC分类号： H01L29/06 ,  H03K17/12 ,  H01L29/423 ,  H01L29/78 ,  H01L29/10 ,  H01L29/739 ,  H01L29/16 ,  H01L29/417 ,  H01L29/40

摘要： Power switching devices include a semiconductor layer structure that has an active region and an inactive region. The active region includes a plurality of unit cells and the inactive region includes a field insulating layer on the semiconductor layer structure and a gate bond pad on the field insulating layer opposite the semiconductor layer structure. A gate insulating pattern is provided on the semiconductor layer structure between the active region and the field insulating layer, and at least one source/drain contact is provided on the semiconductor layer structure between the gate insulating pattern and the field insulating layer.