公开(公告)号：US11075264B2

公开(公告)日：2021-07-27

申请号：US15168310

申请日：2016-05-31

申请人： Cree, Inc.

发明人： Edward Robert Van Brunt ,  Alexander V. Suvorov ,  Vipindas Pala ,  Daniel J. Lichtenwalner ,  Qingchun Zhang

IPC分类号： H01L29/06 ,  H01L29/16 ,  H01L29/04 ,  H01L29/66 ,  H01L29/872 ,  H01L21/04 ,  H01L29/78 ,  H01L29/10

摘要： Semiconductor devices include a silicon carbide drift region having an upper portion and a lower portion. A first contact is on the upper portion of the drift region and a second contact is on the lower portion of the drift region. The drift region includes a superjunction structure that includes a p-n junction that is formed at an angle of between 10° and 30° from a plane that is normal to a top surface of the drift region. The p-n junction extends within +/−1.5° of a crystallographic axis of the silicon carbide material forming the drift region.

公开(公告)号：US20190043980A1

公开(公告)日：2019-02-07

申请号：US16148214

申请日：2018-10-01

申请人： Cree, Inc.

发明人： Qingchun Zhang ,  Brett Hull

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/417 ,  H01L29/66

摘要： A transistor device having a deep recessed P+ junction is disclosed. The transistor device may comprise a gate and a source on an upper surface of the transistor device, and may include at least one doped well region, wherein the at least one doped well region has a first conductivity type that is different from a conductivity type of a source region within the transistor device and the at least one doped well region is recessed from the upper surface of the transistor device by a depth. The deep recessed P+ junction may be a deep recessed P+ implanted junction within a source contact area. The deep recessed P+ junction may be deeper than a termination structure in the transistor device. The transistor device may be a Silicon Carbide (SiC) MOSFET device.

公开(公告)号：US10115815B2

公开(公告)日：2018-10-30

申请号：US13730068

申请日：2012-12-28

申请人： Cree, Inc.

发明人： Qingchun Zhang ,  Brett Hull

IPC分类号： H01L29/772 ,  H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/417 ,  H01L29/08

摘要： A transistor device having a deep recessed P+ junction is disclosed. The transistor device may comprise a gate and a source on an upper surface of the transistor device, and may include at least one doped well region, wherein the at least one doped well region has a first conductivity type that is different from a conductivity type of a source region within the transistor device and the at least one doped well region is recessed from the upper surface of the transistor device by a depth. The deep recessed P+ junction may be a deep recessed P+ implanted junction within a source contact area. The deep recessed P+ junction may be deeper than a termination structure in the transistor device. The transistor device may be a Silicon Carbide (SIC) MOSFET device.

公开(公告)号：US09865750B2

公开(公告)日：2018-01-09

申请号：US14810678

申请日：2015-07-28

申请人： Cree, Inc.

发明人： Jason Patrick Henning ,  Qingchun Zhang ,  Sei-Hyung Ryu ,  Anant Kumar Agarwal ,  John Williams Palmour ,  Scott Allen

IPC分类号： H01L29/872 ,  H01L29/861 ,  H01L29/06

CPC分类号： H01L29/872 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/1608 ,  H01L29/8611 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/00 ,  H01L2224/05552

摘要： The present disclosure generally relates to a Schottky diode that has a substrate, a drift layer provided over the substrate, and a Schottky layer provided over an active region of the drift layer. The metal for the Schottky layer and the semiconductor material for the drift layer are selected to provide a low barrier height Schottky junction between the drift layer and the Schottky layer.

公开(公告)号：US09831355B2

公开(公告)日：2017-11-28

申请号：US15082888

申请日：2016-03-28

申请人： Cree, Inc.

发明人： Qingchun Zhang

IPC分类号： H01L29/15 ,  H01L29/872 ,  H01L29/06 ,  H01L29/16 ,  H01L29/47 ,  H01L29/66

CPC分类号： H01L29/872 ,  H01L29/0619 ,  H01L29/0684 ,  H01L29/1608 ,  H01L29/47 ,  H01L29/6606

摘要： The present disclosure relates to a Schottky diode having a drift layer and a Schottky layer. The drift layer is predominantly doped with a doping material of a first conductivity type and has a first surface associated with an active region. The Schottky layer is provided over the active region of the first surface to form a Schottky junction. A plurality of junction barrier elements are formed in the drift layer below the Schottky junction, and a plurality of central implants are also formed in the drift layer below the Schottky junction. In certain embodiments, at least one central implant is provided between each adjacent pair of junction barrier elements.

公开(公告)号：US09530844B2

公开(公告)日：2016-12-27

申请号：US13730133

申请日：2012-12-28

申请人： Cree, Inc.

发明人： Qingchun Zhang ,  Brett Hull

IPC分类号： H01L29/732 ,  H01L29/66 ,  H01L29/16 ,  H01L29/739 ,  H01L29/749 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08

CPC分类号： H01L29/7802 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66333 ,  H01L29/66378 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/749 ,  H01L29/7827 ,  H01L29/7828

摘要： A transistor device having reduced electrical field at the gate oxide interface is disclosed. In one embodiment, the transistor device comprises a gate, a source, and a drain, wherein the gate is at least partially in contact with a gate oxide. The transistor device has a P+ region within a JFET region of the transistor device in order to reduce an electrical field on the gate oxide.

摘要翻译： 公开了一种在栅极氧化物界面处具有减小的电场的晶体管器件。 在一个实施例中，晶体管器件包括栅极，源极和漏极，其中栅极至少部分地与栅极氧化物接触。 晶体管器件在晶体管器件的JFET区域内具有P +区域，以便减小栅极氧化物上的电场。

公开(公告)号：US09318624B2

公开(公告)日：2016-04-19

申请号：US13686119

申请日：2012-11-27

申请人： Cree, Inc.

发明人： Qingchun Zhang

IPC分类号： H01L29/47 ,  H01L29/872 ,  H01L29/66 ,  H01L29/06 ,  H01L29/16

CPC分类号： H01L29/872 ,  H01L29/0619 ,  H01L29/0684 ,  H01L29/1608 ,  H01L29/47 ,  H01L29/6606

摘要： The present disclosure relates to a Schottky diode having a drift layer and a Schottky layer. The drift layer is predominantly doped with a doping material of a first conductivity type and has a first surface associated with an active region. The Schottky layer is provided over the active region of the first surface to form a Schottky junction. A plurality of junction barrier elements are formed in the drift layer below the Schottky junction, and a plurality of central implants are also formed in the drift layer below the Schottky junction. In certain embodiments, at least one central implant is provided between each adjacent pair of junction barrier elements.

摘要翻译： 本公开涉及具有漂移层和肖特基层的肖特基二极管。 漂移层主要掺杂有第一导电类型的掺杂材料，并且具有与有源区相关联的第一表面。 肖特基层设置在第一表面的有源区上以形成肖特基结。 在肖特基结下方的漂移层中形成多个结屏障元件，并且在肖特基结下方的漂移层中也形成多个中心植入物。 在某些实施例中，至少一个中心植入物设置在每对相邻的接合屏障元件之间。

公开(公告)号：US20140183553A1

公开(公告)日：2014-07-03

申请号：US13730133

申请日：2012-12-28

申请人： CREE, INC.

发明人： Qingchun Zhang ,  Brett Hull

IPC分类号： H01L29/78 ,  H01L29/16

CPC分类号： H01L29/7802 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66333 ,  H01L29/66378 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/749 ,  H01L29/7827 ,  H01L29/7828

摘要： A transistor device having reduced electrical field at the gate oxide interface is disclosed. In one embodiment, the transistor device comprises a gate, a source, and a drain, wherein the gate is at least partially in contact with a gate oxide. The transistor device has a P+ region within a JFET region of the transistor device in order to reduce an electrical field on the gate oxide.

摘要翻译： 公开了一种在栅极氧化物界面处具有减小的电场的晶体管器件。 在一个实施例中，晶体管器件包括栅极，源极和漏极，其中栅极至少部分地与栅极氧化物接触。 晶体管器件在晶体管器件的JFET区域内具有P +区域，以便减小栅极氧化物上的电场。

公开(公告)号：US20140183552A1

公开(公告)日：2014-07-03

申请号：US13730068

申请日：2012-12-28

申请人： CREE, INC.

发明人： Qingchun Zhang ,  Brett Hull

IPC分类号： H01L29/16 ,  H01L29/66

CPC分类号： H01L29/1608 ,  H01L29/0619 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/66477 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7828

摘要： A transistor device having a deep recessed P+ junction is disclosed. The transistor device may comprise a gate and a source on an upper surface of the transistor device, and may include at least one doped well region, wherein the at least one doped well region has a first conductivity type that is different from a conductivity type of a source region within the transistor device and the at least one doped well region is recessed from the upper surface of the transistor device by a depth. The deep recessed P+ junction may be a deep recessed P+ implanted junction within a source contact area. The deep recessed P+ junction may be deeper than a termination structure in the transistor device. The transistor device may be a Silicon Carbide (SIC) MOSFET device.

摘要翻译： 公开了具有深凹陷P +结的晶体管器件。 晶体管器件可以包括在晶体管器件的上表面上的栅极和源极，并且可以包括至少一个掺杂阱区域，其中至少一个掺杂阱区域具有不同于导电类型的第一导电类型 晶体管器件内的源区和至少一个掺杂阱区从晶体管器件的上表面凹入深度。 深凹陷的P +结可以是源接触区域内的深凹陷P +注入结。 深凹陷的P +结可以比晶体管器件中的端接结构更深。 晶体管器件可以是碳化硅（SIC）MOSFET器件。

公开(公告)号：US20140145289A1

公开(公告)日：2014-05-29

申请号：US13686119

申请日：2012-11-27

申请人： CREE, INC.

发明人： Qingchun Zhang

IPC分类号： H01L29/872

CPC分类号： H01L29/872 ,  H01L29/0619 ,  H01L29/0684 ,  H01L29/1608 ,  H01L29/47 ,  H01L29/6606

摘要： The present disclosure relates to a Schottky diode having a drift layer and a Schottky layer. The drift layer is predominantly doped with a doping material of a first conductivity type and has a first surface associated with an active region. The Schottky layer is provided over the active region of the first surface to form a Schottky junction. A plurality of junction barrier elements are formed in the drift layer below the Schottky junction, and a plurality of central implants are also formed in the drift layer below the Schottky junction. In certain embodiments, at least one central implant is provided between each adjacent pair of junction barrier elements.

摘要翻译： 本公开涉及具有漂移层和肖特基层的肖特基二极管。 漂移层主要掺杂有第一导电类型的掺杂材料，并且具有与有源区相关联的第一表面。 肖特基层设置在第一表面的有源区上以形成肖特基结。 在肖特基结下方的漂移层中形成多个结屏障元件，并且在肖特基结下方的漂移层中也形成多个中心植入物。 在某些实施例中，至少一个中心植入物设置在每对相邻的接合屏障元件之间。