Invention Grant
- Patent Title: Method of forming complementary metal oxide semiconductor device with work function layer
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Application No.: US15194577Application Date: 2016-06-28
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Publication No.: US09721840B2Publication Date: 2017-08-01
- Inventor: Chien-Ming Lai , Chien-Chung Huang , Yu-Ting Tseng , Ya-Huei Tsai , Yu-Ping Wang
- Applicant: UNITED MICROELECTRONICS CORP.
- Applicant Address: TW Hsin-Chu
- Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee Address: TW Hsin-Chu
- Agent Winston Hsu
- Priority: CN201410524514 20140930
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L21/28 ; H01L21/8238 ; H01L27/092 ; H01L29/49 ; H01L29/66 ; H01L21/283 ; H01L21/321 ; H01L21/3213 ; H01L29/51 ; H01L29/78
Abstract:
The present invention provides a complementary metal oxide semiconductor device, comprising a PMOS and an NMOS. The PMOS has a P type metal gate, which comprises a bottom barrier layer, a P work function metal (PWFM) layer, an N work function tuning (NWFT) layer, an N work function metal (NWFM) layer and a metal layer. The NMOS has an N type metal gate, which comprises the NWFT layer, the NWFM layer and the low-resistance layer. The present invention further provides a method of forming the same.
Public/Granted literature
- US20160307805A1 METHOD OF FORMING COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICE Public/Granted day:2016-10-20
Information query
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