Invention Grant
- Patent Title: Fringe capacitance reduction for replacement gate CMOS
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Application No.: US15093881Application Date: 2016-04-08
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Publication No.: US09780192B2Publication Date: 2017-10-03
- Inventor: Hiroaki Niimi , Mahalingam Nandakumar
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Jacqueline J. Garner; Charles A. Brill; Frank D. Cimino
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/51 ; H01L21/3105 ; H01L21/3213 ; H01L21/311 ; H01L21/321 ; H01L21/02 ; H01L21/28 ; H01L21/8234 ; H01L21/8238 ; H01L29/49 ; H01L27/092 ; H01L29/423 ; H01L29/78 ; H01L21/32
Abstract:
A replacement metal gate transistor structure and method with thin silicon nitride sidewalls and with little or no high-k dielectric on the vertical sidewalls of the replacement gate transistor trench.
Public/Granted literature
- US20160233312A1 FRINGE CAPACITANCE REDUCTION FOR REPLACEMENT GATE CMOS Public/Granted day:2016-08-11
Information query
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