Invention Grant
- Patent Title: Clock generation system with dynamic distribution bypass mode
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Application No.: US15212044Application Date: 2016-07-15
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Publication No.: US09836078B2Publication Date: 2017-12-05
- Inventor: Allan Feldman , Nasser Kurd , Mark Neidengard , Vaughn Grossnickle , Praveen Mosalikanti
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Green, Howard & Mughal LLP
- Main IPC: G06F1/10
- IPC: G06F1/10 ; H03K5/15 ; G06F1/04 ; H03L7/06 ; H03L7/08 ; H03L7/083 ; G06F1/08
Abstract:
In some embodiments, a tight loop mode is provided in which most, if not all of, the clock distribution circuitry may be bypassed during an initial frequency lock stage.
Public/Granted literature
- US20160327974A1 CLOCK GENERATION SYSTEM WITH DYNAMIC DISTRIBUTION BYPASS MODE Public/Granted day:2016-11-10
Information query
