-
公开(公告)号：US10824764B2
公开(公告)日：2020-11-03
申请号：US16020918
申请日：2018-06-27
Applicant: Intel Corporation
Inventor： Nasser Kurd , Praveen Mosalikanti , Thripthi Hegde , Mark Neidengard , Vaughn Grossnickle , Qi S. Wang , Kandadai Ramesh
Abstract: An apparatus is provided for autonomous security and functional safety (FUSA) of clock and voltages. The apparatus may include: a multiplexer having a first input communicatively coupled to a pin to receive a first clock external to a die, and a second input coupled to an output of a divider; an oscillator to provide a second clock; and a counter coupled to an output of the multiplexer and the oscillator, wherein the counter is to operate with the second clock and is to determine a frequency of the first clock. The apparatus may further include a voltage monitor circuitry for monitoring voltage(s) for FUSA, a reference generator for FUSA, a duty cycle monitor for FUSA, a frequency degradation monitor for FUSA, and a phase error degradation monitor for FUSA.
-
公开(公告)号：US20200004990A1
公开(公告)日：2020-01-02
申请号：US16020918
申请日：2018-06-27
Applicant: Intel Corporation
Inventor： Nasser Kurd , Praveen Mosalikanti , Thripthi Hegde , Mark Neidengard , Vaughn Grossnickle , Qi S. Wang , Kandadai Ramesh
Abstract: An apparatus is provided for autonomous security and functional safety (FUSA) of clock and voltages. The apparatus may include: a multiplexer having a first input communicatively coupled to a pin to receive a first clock external to a die, and a second input coupled to an output of a divider; an oscillator to provide a second clock; and a counter coupled to an output of the multiplexer and the oscillator, wherein the counter is to operate with the second clock and is to determine a frequency of the first clock. The apparatus may further include a voltage monitor circuitry for monitoring voltage(s) for FUSA, a reference generator for FUSA, a duty cycle monitor for FUSA, a frequency degradation monitor for FUSA, and a phase error degradation monitor for FUSA.
-
公开(公告)号：US09836078B2
公开(公告)日：2017-12-05
申请号：US15212044
申请日：2016-07-15
Applicant: Intel Corporation
Inventor： Allan Feldman , Nasser Kurd , Mark Neidengard , Vaughn Grossnickle , Praveen Mosalikanti
CPC classification number: G06F1/10 , G06F1/04 , G06F1/08 , H03K5/15 , H03L7/06 , H03L7/08 , H03L7/0802 , H03L7/083
Abstract: In some embodiments, a tight loop mode is provided in which most, if not all of, the clock distribution circuitry may be bypassed during an initial frequency lock stage.
-
公开(公告)号：US11461504B2
公开(公告)日：2022-10-04
申请号：US17087414
申请日：2020-11-02
Applicant: Intel Corporation
Inventor： Nasser Kurd , Praveen Mosalikanti , Thripthi Hegde , Mark Neidengard , Vaughn Grossnickle , Qi S. Wang , Kandadai Ramesh
Abstract: An apparatus is provided for autonomous security and functional safety (FUSA) of clock and voltages. The apparatus may include: a multiplexer having a first input communicatively coupled to a pin to receive a first clock external to a die, and a second input coupled to an output of a divider; an oscillator to provide a second clock; and a counter coupled to an output of the multiplexer and the oscillator, wherein the counter is to operate with the second clock and is to determine a frequency of the first clock. The apparatus may further include a voltage monitor circuitry for monitoring voltage(s) for FUSA, a reference generator for FUSA, a duty cycle monitor for FUSA, a frequency degradation monitor for FUSA, and a phase error degradation monitor for FUSA.
-
公开(公告)号：US20210049307A1
公开(公告)日：2021-02-18
申请号：US17087414
申请日：2020-11-02
Applicant: Intel Corporation
Inventor： Nasser Kurd , Praveen Mosalikanti , Thripthi Hegde , Mark Neidengard , Vaughn Grossnickle , Qi S. Wang , Kandadai Ramesh
Abstract: An apparatus is provided for autonomous security and functional safety (FUSA) of clock and voltages. The apparatus may include: a multiplexer having a first input communicatively coupled to a pin to receive a first clock external to a die, and a second input coupled to an output of a divider; an oscillator to provide a second clock; and a counter coupled to an output of the multiplexer and the oscillator, wherein the counter is to operate with the second clock and is to determine a frequency of the first clock. The apparatus may further include a voltage monitor circuitry for monitoring voltage(s) for FUSA, a reference generator for FUSA, a duty cycle monitor for FUSA, a frequency degradation monitor for FUSA, and a phase error degradation monitor for FUSA.
-
Patent Agency Ranking
公开(公告)号：US10320395B2
公开(公告)日：2019-06-11
申请号：US15414408
申请日：2017-01-24
Applicant: Intel Corporation
Inventor： Mark Neidengard
Abstract: An apparatus is described. The apparatus includes a counter circuit having ordered state element circuits where a respective clock input of a state element circuit is fed by a data output of a preceding lower ordered bit state element. The counter circuit also being programmable to enable different amounts to be counted by the counter circuit, wherein respective reload values for the amounts are received at the state elements as a respective asynchronous set or reset.
-
公开(公告)号：US09450589B2
公开(公告)日：2016-09-20
申请号：US14126005
申请日：2013-06-28
Applicant: Intel Corporation
Inventor： Allan Feldman , Nasser Kurd , Mark Neidengard , Vaughn Grossnickle , Praveen Mosalikanti
CPC classification number: G06F1/10 , G06F1/04 , G06F1/08 , H03K5/15 , H03L7/06 , H03L7/08 , H03L7/0802 , H03L7/083
Abstract: In some embodiments, a tight loop mode is provided is which most, if not all of, the clock distribution circuitry may be bypassed during an initial frequency lock stage.
Abstract translation: 在一些实施例中，提供紧密环路模式，其中大多数（如果不是全部）时钟分配电路可以在初始频率锁定阶段期间被旁路。
-
公开(公告)号：US10790838B1
公开(公告)日：2020-09-29
申请号：US16412165
申请日：2019-05-14
Applicant: Intel Corporation
Inventor： Praveen Mosalikanti , Vaughn J. Grossnickle , Syed Feruz Syed Farooq , Mark Neidengard , Nasser A. Kurd
Abstract: Dynamic voltage frequency scaling to transition to a target clock frequency and associated target voltage is provided. Dynamic voltage frequency scaling to a different clock frequency is performed by gradually changing the clock frequency using discrete variable-size steps, while dynamically switching to faster or slower reference clock frequencies as appropriate to harmonize the frequency trajectory with system requirements.
-
公开(公告)号：US09876491B2
公开(公告)日：2018-01-23
申请号：US14929154
申请日：2015-10-30
Applicant: INTEL CORPORATION
Inventor： Mark Neidengard , Vaughn Grossnickle , Nasser Kurd , Jeffrey Krieger
CPC classification number: H03K5/1565 , H03K3/0315
Abstract: Described herein are apparatus, method, and system for re-synthesizing a clock signal. The apparatus comprises: a first logic unit to detect a rising edge of an input clock signal and for generating a rising edge of an output clock signal based on the detected rising edge of the input clock signal, the input clock signal having a non-50% duty cycle and a first period; and a second logic unit to compute a falling edge of the output clock signal according to the detected rising edge of the input clock signal, the falling edge of the output clock signal being near half of the first period.
-
公开(公告)号：US20160327974A1
公开(公告)日：2016-11-10
申请号：US15212044
申请日：2016-07-15
Applicant: Intel Corporation
Inventor： Allan Feldman , Nasser Kurd , Mark Neidengard , Vaughn Grossnickle , Praveen Mosalikanti
CPC classification number: G06F1/10 , G06F1/04 , G06F1/08 , H03K5/15 , H03L7/06 , H03L7/08 , H03L7/0802 , H03L7/083
Abstract: In some embodiments, a tight loop mode is provided in which most, if not all of, the clock distribution circuitry may be bypassed during an initial frequency lock stage.
Abstract translation: 在一些实施例中，提供紧密环路模式，其中大多数（如果不是全部）时钟分配电路可能在初始频率锁定阶段期间被旁路。
-
-
-
-
-
-
-
-
-
Search Results
11
records
(took 0.014 seconds)
