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    DEVICE, METHOD AND SYSTEM FOR ON-CHIP GENERATION OF A REFERENCE CLOCK SIGNAL
    1.
    发明申请
    DEVICE, METHOD AND SYSTEM FOR ON-CHIP GENERATION OF A REFERENCE CLOCK SIGNAL 审中-公开

    公开(公告)号：US20200005728A1

    公开(公告)日：2020-01-02

    申请号：US16019924

    申请日：2018-06-27

    Applicant: Intel Corporation

    Inventor： Nasser Kurd ,  Daniel Ragland ,  Ameya Ambardekar ,  John Fallin ,  Praveen Mosalikanti ,  Vaughn J. Grossnickle

    IPC: G09G5/00 ,  H03L7/08 ,  G06F1/04 ,  G06F1/26

    Abstract: Techniques and mechanisms for an integrated circuit (IC) chip to generate a clock signal for use by one or more resources of the IC chip. In an embodiment, a clock signal is generated with phase-locked loop (PLL) circuitry of an IC chip based on a cyclical signal which is provided to the IC chip by an external source. A supply voltage provided to the PLL circuitry is automatically updated based on one of a requested frequency for the clock signal, a frequency of the received cyclical signal, or a voltage of a control signal used by a voltage controlled oscillator of the PLL circuitry. In another embodiment, a series of incremental changes to a frequency of the clock signal is automatically performed according to a predefined overclocking scheme or underclocking scheme.

    INTELLECTUAL PROPERTY SECURITY LOCKING APPARATUS AND METHOD
    4.
    发明申请
    INTELLECTUAL PROPERTY SECURITY LOCKING APPARATUS AND METHOD 有权

    公开(公告)号：US20220200655A1

    公开(公告)日：2022-06-23

    申请号：US17132893

    申请日：2020-12-23

    Applicant: Intel Corporation

    Inventor： Mohamed A. Abdelmoneum ,  Nasser Kurd ,  Thripthi Hegde ,  Narayan Srinivasa ,  Peter Sagazio

    IPC: H04B1/7156 ,  H04B1/7136 ,  H04B1/7143 ,  H04L9/08

    Abstract: A clock buffer or driver is gated pending reception of verifiable crypto keys. These clock buffer or divers remain gated, thus disabling a processor from any meaningful function, till crypto keys are decoded, verified, and applied to the clock buffer or driver. A low frequency pseudorandom frequency hopping time sequence is generated and used for randomizing spread-spectrum to modulate a reference clock (or output clock) of a frequency synthesizer. This hopping time sequence holds the key to unlocking the crypto keys. The PWM modulated crypto keys are carried by the hopping time sequence. To decode the PWM modulated crypto keys, the hopping time sequence is used. The reference clock which is modulated with crypto keys in the spread-spectrum is sent to a decoder (in a processor) along with the hopping time sequence. The crypto keys are decoded and then used to un-gate the clock buffer.

    LOW POWER APPARATUS AND METHOD TO MULTIPLY FREQUENCY OF A CLOCK
    5.
    发明申请
    LOW POWER APPARATUS AND METHOD TO MULTIPLY FREQUENCY OF A CLOCK 有权

    公开(公告)号：US20210351779A1

    公开(公告)日：2021-11-11

    申请号：US16870405

    申请日：2020-05-08

    Applicant: Intel Corporation

    Inventor： Kuan-Yueh Shen ,  Nasser Kurd

    IPC: H03L7/081 ,  H03L7/07 ,  H03L7/087 ,  H03K5/156

    Abstract: A multi-feedback circuit that compares a duty cycle corrected reference clock fREF, and controls a number of identical delay lines to generate a new clock with a frequency that is a multiple (e.g., 32×, 4×, etc.) of the frequency of fREF with approximately 50% duty cycle (DC). The new clock is used as a reference clock to a phase locked loop (PLL) or a multiplying delay locked loop (MDLL) resulting in shorter lock times for the PLL/MDLL, higher bandwidth for the PLL/MDLL, lower long-term output clock jitter. The multi-feedback circuit can also be used as a low power clock generator.

    LOW LATENCY ADAPTIVE CLOCKING
    9.
    发明申请
    LOW LATENCY ADAPTIVE CLOCKING 审中-公开

    公开(公告)号：US20200272197A1

    公开(公告)日：2020-08-27

    申请号：US16637646

    申请日：2018-09-06

    Applicant: Intel Corporation

    Inventor： Praveen Mosalikanti ,  Nasser Kurd

    IPC: G06F1/10 ,  H03L7/093 ,  H03L7/099

    Abstract: An apparatus is provided for low latency adaptive clocking, the apparatus comprises: a first power supply rail to provide a first power; a second power supply rail to provide a second power; a third power supply rail to provide a third power; a voltage divider coupled to the first, second, and third power supply rails; a bias generator coupled to voltage divider and the third power supply rail; an oscillator coupled to the bias generator and the first supply rail; and a clock distribution network to provide an output of the oscillator to one or more logics, wherein the clock distribution network is coupled to the second power supply rail.

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